Array Substrate Gate Electrode Noise Shielding via Vertical Capacitor Stacking
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Solution Overview
Problem
In existing display technologies, the gate electrode of the driving transistor is susceptible to noise interference due to the larger area of the conductive portion required for the capacitor, leading to increased parasitic capacitance and reduced noise shielding effectiveness.
Innovation Solution
The array substrate design includes a slot on the buffer layer, reducing the distance between the conductive portions and allowing a smaller area for the capacitor electrodes, which are shielded by a conductive portion with a smaller area, thereby reducing noise interference and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductive portion area is increased to form a capacitor structure, then the capacitor can be formed, but the gate electrode becomes more susceptible to noise interference and parasitic capacitance increases
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure by placing the capacitor electrode in a different layer (second conductive layer) above the gate electrode (first conductive layer), separated by a dielectric layer. This vertical arrangement reduces the lateral area requirement while maintaining capacitance functionality and improving noise shielding.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the capacitor electrode and the gate electrode. This dielectric layer serves as a shielding barrier that reduces noise interference and parasitic capacitance coupling between the capacitor and gate electrode, while still allowing the capacitor to function.
2Reliability
If the conductive portion area is increased, then the capacitor electrode area increases, but the noise shielding effectiveness decreases
Solution Approach 1:
The patent moves the capacitor electrode to a different layer (second conductive layer) vertically above the gate electrode, separated by a dielectric layer. This vertical stacking approach maintains adequate noise shielding while reducing the lateral area requirement for the capacitor electrode.
Solution Approach 2:
The dielectric layer positioned between the capacitor electrode and gate electrode acts as an intermediary shielding barrier, effectively reducing noise interference and improving noise shielding effectiveness without requiring a larger electrode area.
3Object-affected harmful factors
If the distance between conductive portions is reduced, then the parasitic capacitance is reduced, but the layout density increases
Solution Approach 1:
The patent utilizes the vertical dimension by stacking the capacitor electrode (second conductive layer) above the gate electrode (first conductive layer) with a dielectric layer in between. This vertical arrangement reduces the lateral footprint and layout density while maintaining reduced parasitic capacitance through optimized vertical spacing.
Data Source
AI summary
An array substrate includes a pixel driving circuit, a base substrate, a first conductive layer, a first dielectric layer, a second conductive layer, and a data line. The pixel driving circuit includes a driving transistor, a first transistor, a capacitor, and a second transistor. The first conductive layer is laminated at a side of the base substrate and includes a first conductive portion. The first dielectric layer is laminated at a side of the first conductive layer away from the base substrate. The second conductive layer is laminated at a side of the first dielectric layer away from the base substrate, and includes a fourth gate line. The first conductive layer further includes a first gate line. An orthographic projection of the first gate line on the base substrate is located between orthographic projections of the fourth gate line and the first conductive portion on the base substrate.