Array Substrate Gate Notch Layout for Lower TFT Load Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In display devices with multiple thin-film transistors arranged in close proximity, the increased load capacitance in the gaps between them can adversely affect display quality and the service life of the device, reducing its reliability.
Innovation Solution
The array substrate incorporates a gate electrode with a notch formed in the region between semiconductor members, which reduces the parasitic capacitance between the source electrode and the gate electrodes, thereby minimizing the load capacitance on the signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If multiple thin-film transistors are arranged in close proximity, then heat generation is suppressed, but load capacitance increases
Solution Approach 1:
The gate electrode is divided into multiple gate electrodes corresponding to each semiconductor member. By segmenting the gate electrode structure, the parasitic capacitance between the source electrode and gate electrode is reduced, thereby decreasing the load capacitance on signal lines while maintaining the close proximity arrangement of multiple thin-film transistors for heat suppression
Solution Approach 2:
The gate electrode is configured to overlap only with the respective semiconductor member and not with adjacent semiconductor members. This local quality approach ensures that each gate electrode interacts only with its intended semiconductor member, minimizing parasitic capacitance in gap regions while maintaining effective transistor operation
2Productivity
If multiple thin-film transistors are arranged in close proximity, then device integration is improved, but display quality deteriorates
Solution Approach 1:
The gate electrode is segmented into multiple separate gate electrodes, each corresponding to a specific semiconductor member. This segmentation reduces parasitic capacitance effects that would otherwise degrade display quality, while still allowing high-density arrangement of thin-film transistors for improved device integration
Solution Approach 2:
The harmful parasitic capacitance effect is extracted or removed by configuring the gate electrode to not overlap with adjacent semiconductor members. This extraction of the harmful capacitive coupling allows high-density transistor arrangement without compromising display quality
Data Source
AI summary
According to one embodiment, an array substrate includes a transparent substrate, a linear source electrode disposed on the transparent substrate, a linear drain electrode disposed on a same layer as that of the source electrode, at least two semiconductor members connected in parallel between the source electrode and the drain electrode, and a gate electrode overlapping the source electrode, the drain electrode and the at least two semiconductor members, and the gate electrode has a notch formed in a region between the at least two semiconductor members.