Array Substrate Gate Protection for Uniform Insulating Layer
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Solution Overview
Problem
Liquid crystal display devices based on fringe field switching (FFS) mode face issues with non-uniform thickness of the gate insulating layer, leading to increased voltage fluctuation, flicker, abnormal displays, and high power consumption due to smaller storage capacitance and exposure of the gate during etching processes.
Innovation Solution
An array substrate design with a protective layer covering the gate to prevent etching, ensuring uniformity of the gate insulating layer thickness, and a method involving specific layer formations and etching steps to maintain the integrity of the gate and improve capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the gate insulating layer is etched before ashing the photoresist layer to thin the dielectric layer, then the thickness of the dielectric layer is reduced, but the etching rate is difficult to control resulting in poor thickness uniformity
Solution Approach 1:
The patent applies preliminary action by forming the gate protecting unit on the gate electrode before performing any etching processes. This protective structure is prepared in advance to prevent unintended etching of the gate insulating layer during subsequent photoresist ashing and source-drain layer etching, thereby ensuring uniform thickness control without compromising gate integrity
Solution Approach 2:
The gate protecting unit serves as an intermediary element between the gate electrode and the etching environment. This intermediate protective layer selectively shields the gate insulating layer during etching processes, allowing precise control of dielectric layer thickness while preventing uncontrolled etching of the gate region
2Length of stationary object
If the gate insulating layer is completely removed before ashing the photoresist layer, then the dielectric layer thickness is reduced, but the gate is exposed and easily etched resulting in array substrate failure
Solution Approach 1:
The patent applies preliminary action by forming the gate protecting unit on the gate electrode before performing any etching processes. This protective structure is prepared in advance to prevent unintended etching of the gate insulating layer during subsequent photoresist ashing and source-drain layer etching, thereby ensuring uniform thickness control without compromising gate integrity
Solution Approach 2:
The gate protecting unit provides preliminary anti-action by pre-establishing a protective barrier against etching attacks. This preventive measure counteracts the potential harmful effect of exposed gate etching during the manufacturing process, eliminating the risk of array substrate failure while allowing complete removal of the gate insulating layer where needed
Data Source
AI summary
An array substrate includes a substrate, a first conductor layer, a protective layer, a gate insulating layer, an active layer, and a second conductor layer. The first conductor layer includes a gate in a thin film transistor area. The protective layer is disposed on the first conductor layer and includes a gate protecting unit on the gate. The gate insulating layer is disposed on the gate protecting unit. The active layer is disposed on the gate insulating layer and in a thin film transistor area. The second conductor layer is disposed on a side of the active layer away from the substrate and includes a source and a drain at intervals in the thin film transistor area.