Array Substrate Gate Electrode Protrusion for TFT Reliability
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Solution Overview
Problem
The existing array substrates for liquid crystal display (LCD) and organic electroluminescent display (OELD) devices face issues with the degradation of thin film transistors (TFTs) due to thickness differences in the active layer, low carrier mobility, and increased production costs associated with doping processes, which affect the performance and reliability of the devices.
Innovation Solution
The array substrate design includes intrinsic polycrystalline silicon active layers with impurity-doped polycrystalline silicon gate electrodes, utilizing an interlayer insulating layer as an etch-stopper to maintain uniform thickness and prevent degradation, and reduces the number of contact holes to improve aperture ratio and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the active layer thickness is reduced to improve aperture ratio, then the aperture ratio is improved, but the TFT properties are degraded due to insufficient active layer thickness
Solution Approach 1:
The patent applies local quality by forming a protrusion structure on the gate electrode that locally concentrates the electric field overhanging the active layer. This localized enhancement of electric field strength compensates for the reduced active layer thickness, maintaining sufficient carrier induction and TFT performance while allowing overall thickness reduction for improved aperture ratio.
2Reliability
If doping processes are added to improve carrier mobility, then carrier mobility is improved, but production costs and process complexity increase
Solution Approach 1:
The patent extracts and eliminates the doping process from the manufacturing sequence by using intrinsic (undoped) amorphous silicon for the active layer. Carrier mobility is improved instead through the protrusion structure on the gate electrode that enhances the electric field, thereby avoiding the complexity and cost of doping processes while maintaining high carrier mobility.
3Area of stationary object
If the number of contact holes is reduced to improve aperture ratio, then the aperture ratio is improved, but the electrical connectivity and reliability may be compromised
Solution Approach 1:
The patent addresses electrical connectivity by extending the source and drain electrodes in the vertical direction (thickness direction) to form protruding portions that extend toward the gate electrode. This dimensional extension provides multiple contact points and redundant conduction paths, ensuring reliable electrical connectivity while maintaining a reduced number of contact holes for improved aperture ratio.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the mobility of carriers in the active layers, prevents degradation of TFT properties, and reduces production costs by maintaining uniform active layer thickness and minimizing contact holes, thereby improving the performance and efficiency of the array substrate.
Implementation Method 1
a protrusion structure on a gate electrode, thereby enhancing an electric field overhanging an active layer
Implementation Method 2
where an intrinsic amorphous silicon layer is transformed into an intrinsic polycrystalline silicon layer
Data Source
AI summary
An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.