Array Substrate Gate Line Recess Layout for Lower Signal Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In large-sized liquid crystal displays, the charging of coupling capacitances between gate and data lines leads to significant signal delay in gate lines due to increased time required for charging, which is exacerbated by the presence of coupling capacitances between the gate and source/drain of thin film transistors.
Innovation Solution
The array substrate incorporates a widening portion with a recess structure in the gate lines between adjacent data lines, reducing the resistance and time needed to charge coupling capacitances, while the recess structure overlaps with the drain of the thin film transistor, minimizing coupling capacitances between the drain and gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the gate line width is increased to reduce resistance and charging time, then the signal delay is reduced, but the coupling capacitance between gate lines and data lines increases
Solution Approach 1:
The gate line width is locally adjusted by adding a widening portion with a recess structure only in specific regions between data lines, rather than uniformly increasing the width across the entire gate line. This localized modification reduces resistance and charging time in critical areas while avoiding increased coupling capacitance at intersections with data lines.
2Speed
If the gate line width is uniformly increased, then the resistance decreases and charging speed improves, but the area occupied by the gate line increases
Solution Approach 1:
Instead of uniformly increasing the gate line width across its entire length, the invention applies width modification only in specific segments where recess structures are formed between data lines. This localized approach reduces the total area occupied by the gate line while still achieving improved charging speed in the critical regions where the widening portions are implemented.
3Object-generated harmful factors
If the recess structure is positioned to overlap with the drain, then the coupling capacitance between drain and gate line is reduced, but the wiring complexity increases
Solution Approach 1:
The recess structure serves multiple functions simultaneously: it acts as a widening portion to reduce gate line resistance, creates an overlapping region with the drain to reduce coupling capacitance, and provides a pathway for via holes to connect the drain to the pixel electrode. By integrating these multiple functions into a single structural feature, the wiring complexity is minimized while achieving the desired electrical performance improvements.
Data Source
AI summary
An array substrate and a display device are disclosed. The array substrate includes a base substrate, a plurality of gate lines and a plurality of data lines arranged to intersect each other on the base substrate, a pixel electrode arranged in a region defined by an adjacent gate line and an adjacent data line, and a thin film transistor arranged at an intersection of the gate lines and the data lines. A drain of the thin film transistor is connected with the pixel electrode through a via hole. The gate lines further include a widening portion between adjacent data lines. The widening portion comprises a recess structure. An orthogonal projection of the recess structure on the base substrate at least partly overlaps that of the drain of the thin film transistor on the base substrate.