Array Substrate Gate Insulating Layer Recess Design
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Solution Overview
Problem
As display panel sizes increase and resolutions rise, the thickness of copper (Cu) wire gate electrodes in array substrates must be increased to reduce signal delay, but this leads to step coverage issues, causing the gate electrode insulating layer to thicken, which decreases the ON-state current and increases the risk of insufficient panel charging rates.
Innovation Solution
The array substrate is manufactured with a two-step process for gate electrode insulating layers, where a first gate electrode insulating layer with a recess is formed, followed by a gate electrode layer within the recess, and a second gate electrode insulating layer covering it, ensuring controlled thickness ratios to maintain ON-state current and prevent panel charging rate issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of copper (Cu) wire is increased to solve circuit delay problems, then the conductivity is improved, but the step coverage problem causes thickness of gate electrode insulating layers to increase
Solution Approach 1:
The gate electrode insulating layer is segmented into two distinct layers with different thickness specifications. The first layer (100-500 nm) addresses the immediate step coverage challenge, while the second layer provides additional protection. This segmentation enables precise control of insulating layer thickness without being constrained by the Cu wire thickness.
Solution Approach 2:
The invention changes the parameter configuration by introducing a two-layer insulating structure with specific thickness ranges. This parameter optimization allows the use of thicker Cu wires (200-5000 nm) for improved conductivity while maintaining controlled insulating layer thickness through the first layer's recessed design, thereby resolving the manufacturing precision issue.
2Reliability
If thickness of Cu film layers in gate electrode structure is increased to reduce impedance, then the electromigration resistance is improved, but thickness of gate electrode insulating layers increases causing insufficient panel charging rates
Solution Approach 1:
The gate electrode insulating layer is divided into two segments: the first layer optimized for electromigration resistance with controlled thickness (100-500 nm), and the second layer providing additional insulation. This segmentation prevents excessive total insulating thickness that would capacitively slow down panel charging while maintaining adequate electromigration resistance through the first layer's optimized design.
Solution Approach 2:
Different portions of the gate electrode structure receive differentiated insulating treatment. The first gate electrode insulating layer is positioned to provide localized protection against electromigration in critical regions, while the overall two-layer structure maintains total thickness within ranges that preserve panel charging performance. This local quality optimization balances electromigration resistance with charging rate requirements.
Data Source
AI summary
An array substrate and manufacturing method thereof are provided. The array substrate includes: a substrate; a first gate electrode insulating layer disposed on the substrate, wherein the first gate electrode insulating layer has a recess therein; a gate electrode layer disposed in the recess of the first gate electrode insulating layer; a second gate electrode insulating layer covering the first gate electrode insulating layer and the gate electrode layer; and an active layer disposed on the second gate electrode insulating layer.