Array Substrate Gate Line Segmentation for Aperture Rate
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Solution Overview
Problem
In Advanced-Super Dimensional Switching (ADS) technology for display devices, the manufacturing process is complicated due to the need for common electrode lines and gate lines to be either in separate layers or in the same layer, leading to reduced aperture rate and increased connection resistance when via holes are used for connection, affecting the efficiency and quality of the display.
Innovation Solution
The array substrate design includes a gate line with separate segments connected by a bridge and a common electrode line with a connection segment extending through a gap between these segments, allowing direct electrical connection without the need for gate pads and via holes, thus reducing connection resistance and improving aperture rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the common electrode line and gate line are provided in the same layer, then the manufacturing process is simplified, but the aperture rate is reduced and connection resistance is increased
Solution Approach 1:
The gate line is divided into multiple separate segments that are spaced apart from each other. This segmentation allows the common electrode line to extend through the gaps between segments without requiring separate layers or via holes, thus maintaining the same-layer configuration while reducing the obstruction to the aperture area.
Solution Approach 2:
The connection segment of the common electrode line acts as an intermediary that extends through the gap between gate line segments to establish electrical connection. This eliminates the need for via holes and gate pads, directly connecting the common electrode to the gate line segments while maintaining a compact same-layer structure.
2Reliability
If via holes are used to connect the common electrode line with the common electrode, then electrical connection is achieved, but connection resistance increases and manufacturing complexity increases
Solution Approach 1:
The via holes and gate pads are extracted from the structure. Instead of using traditional via hole connections, the common electrode line directly extends through the gap between gate line segments to connect with the common electrode, eliminating the intermediate connection structures and reducing manufacturing complexity.
Solution Approach 2:
The connection is achieved by utilizing the spatial gap between segmented gate line segments in the same layer, rather than creating vertical via holes to different layers. This dimensional approach maintains planarity while achieving electrical connection.
3Reliability
If gate pads and via holes are used for connection, then electrical connection is established, but the aperture rate is reduced
Solution Approach 1:
By segmenting the gate line and spacing segments apart, the design eliminates the need for gate pads, allowing the common electrode line to connect directly through the gaps. This segmentation strategy removes unnecessary structural elements that would otherwise reduce the aperture area.
Solution Approach 2:
Gate pads are extracted from the design. The common electrode line directly extends to connect with gate line segments without requiring gate pads as intermediate connection structures, thereby maximizing the aperture area while maintaining electrical connection.
Data Source
AI summary
The embodiments of the present invention disclose an array substrate, a method for manufacturing the same, and a display device. With the solutions of the embodiments, aperture rate is increased, and gate signal delay caused by increased connection resistance of gate line is alleviated. The array substrate of the present invention includes a thin film transistor; a substrate; a common electrode provided on the substrate; a gate line comprising a plurality of separate segments arranged to be spaced apart from each other and connected with each other through a bridge; and a common electrode line provided to be spaced apart from the gate line, the gate line and the common electrode line being in the same layer, wherein the common electrode line comprises a connection segment extending through a gap between separate segments to electrically connect with the common electrode directly.