Array Substrate Gate Line Segmentation for Signal Delay
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Solution Overview
Problem
Display devices with large size screens face signal delay issues due to longer gate lines, leading to incomplete and distorted images, as driving signals reach pixel units out of sync.
Innovation Solution
An array substrate with parallel conductive structures connected through through holes on an insulating layer, reducing the resistance of gate lines and minimizing signal delay by effectively connecting in parallel with the gate lines, ensuring synchronized signal delivery to pixel units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate line length is increased to accommodate large size screens, then the display area is improved, but the signal delay increases causing image distortion
Solution Approach 1:
The gate line is segmented into multiple sections with different resistance values. The gate line includes a first gate line portion with higher resistance and a second gate line portion with lower resistance, creating non-uniform resistance distribution along the gate line to compensate for signal delay in large display areas
Solution Approach 2:
Different portions of the gate line are assigned different resistance characteristics. The first gate line portion (closer to the gate driver) has higher resistance while the second gate line portion (farther from the gate driver) has lower resistance, optimizing signal delivery at different locations
2Speed
If the gate line resistance is reduced to minimize signal delay, then the signal transmission speed is improved, but the gate line width increases affecting pixel aperture ratio
Solution Approach 1:
The gate line resistance is segmented into non-uniform portions rather than using a uniform wide gate line. This allows achieving lower overall resistance without uniformly increasing gate line width, thereby preserving pixel aperture ratio while improving signal transmission speed
Solution Approach 2:
The gate line width and resistance are locally optimized: the first gate line portion has narrower width (higher resistance) while the second gate line portion has wider width (lower resistance), allowing selective resistance reduction only where needed for signal transmission without affecting overall aperture ratio
Data Source
AI summary
An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a plurality of mutually parallel signal lines, an insulating layer located on a layer in which the plurality of signal lines is located and at least one first conductive structure located on the insulating layer. The insulating layer includes at least two first through holes corresponding to the first conductive structure, and the first conductive structure is electrically connected with the signal lines through the at least two first through holes.