Array Substrate Gate Signal Routing for ESD Protection
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Solution Overview
Problem
In TFT-LCD display panels, the gate signal output line is prone to short circuits due to Electro-Static Discharge (ESD) in the ESD prone area, leading to display quality issues and increased production costs.
Innovation Solution
The array substrate design includes a gate signal output line connected to the gate line at a perpendicular direction, with a jumper pad and a common electrode leading wire, where the gate signal output line makes an angle of 45° to 90° with the gate line, avoiding the ESD prone area and reducing the probability of short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate signal output line is routed through the ESD prone area to connect to the gate line, then the electrical connection is achieved, but the probability of short circuits increases due to ESD
Solution Approach 1:
The patent extracts the gate signal output line from the ESD prone area by routing it through the non-display region instead. The line connects to the gate line at a location away from the ESD prone area, effectively removing it from the harmful environment while maintaining its electrical connection function.
Solution Approach 2:
The patent introduces an intermediary connection structure involving a jumper pad and a specific routing path through the non-display region. This intermediary path acts as a mediator that transfers the gate signal from the shift register to the gate line without exposing the critical signal line to ESD risks in the display region.
2Reliability
If the gate signal output line is routed away from the ESD prone area, then the probability of short circuits decreases, but the line length and routing complexity increase
Solution Approach 1:
The patent merges the gate signal output line routing with the existing non-display region structure. By utilizing the available space in the non-display region for the line routing, the design avoids adding extra complexity while achieving the goal of ESD avoidance. The jumper pad is integrated into this merged structure.
3Reliability
If the gate signal output line is routed away from the ESD prone area, then the probability of short circuits decreases, but the area occupied by the routing increases
Solution Approach 1:
The patent transitions the routing from a two-dimensional plane within the display region to utilizing the third dimension of the non-display region. By routing the gate signal output line in the non-display region and connecting at a perpendicular location, the design effectively uses spatial reorganization to minimize area occupation while avoiding ESD risks.
Data Source
AI summary
Embodiments of the present disclosure provide an array substrate, a display panel, and a display apparatus. The array substrate includes: a display region for displaying an image; a non-display region; a shift register provided in the non-display region; a gate line provided in the display region and extending along a first direction; and a gate signal output line, provided in the non-display region and having a first end and a second end. The first end of the gate signal output line is connected to the shift register, and the second end of the gate signal output line is connected to the gate line at a side of the gate line in a second direction perpendicular to the first direction.