Array Substrate Connection Hole Etching

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Solution Overview

Problem

High-precision display technologies face challenges with dense wiring array substrates, where the large slope angle of connection hole walls in existing manufacturing processes leads to poor connection between metal layers, resulting in disconnection or poor coverage.

Innovation Solution

A method involving the sequential formation of a first metal layer, an insulating layer, and an etching barrier layer on a base substrate, with multiple etching steps to form a connection hole with a reduced slope angle, comprising via holes connected in sequence, allowing a second metal layer to be connected to the first metal layer through the hole.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single etching process is used to form connection holes, then the manufacturing process is simple, but the slope angle of the hole wall becomes large causing poor connection

Engineering Contradiction:
Improveetching process simplicityVSAvoidconnection hole slope angle
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The single etching process is divided into multiple sequential etching steps (first etching, second etching, third etching) with different etching depths and barrier layer configurations. Each etching step creates a portion of the connection hole with controlled slope angle, and the barrier layer is selectively removed or reduced in effective blocking area between steps to enable progressive hole formation with gentler walls.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the insulating layer thickness is increased for better insulation, then the insulation performance improves, but the connection hole formation becomes more difficult and slope angle increases

Engineering Contradiction:
Improveinsulation performanceVSAvoidconnection hole slope angle
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The thick insulating layer is etched in multiple segments through sequential etching steps. The barrier layer serves as a temporary stopper that is selectively removed or reduced between etching steps, allowing the connection hole to progress through the thick insulating layer in controlled portions, maintaining gentle slope angles throughout the entire thickness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier layer is formed on the insulating layer before etching begins, and its effective blocking area is progressively reduced in predetermined stages before each etching step. This preliminary preparation ensures that each etching step encounters the correct barrier layer configuration, enabling controlled hole formation through the thick insulating layer with appropriate slope angles.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces the slope angle of the connection hole walls, improving the connection between metal layers, preventing disconnection and enhancing the precision and reliability of high-precision display technologies.

Implementation Method 1

etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS11537016B2Method of manufacturing array substrate, and array substrate
Publication Date: 2022.12.27 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US11537016B2 patent drawing
  • US11537016B2 patent drawing
  • US11537016B2 patent drawing

AI summary

A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.