Array Substrate In-Plane Connection Aperture Ratio
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Solution Overview
Problem
Conventional liquid crystal display products with common electrodes face challenges in increasing aperture ratio due to inefficient space utilization and light leakage, leading to horizontal stripes and luminance differences in displays.
Innovation Solution
The design includes an array substrate with intersecting data and gate lines forming pixel units, where the drain electrode connection is between or over gate lines, and multiple via holes connect common electrode lines to common electrodes, ensuring uniform black matrix shapes and improved aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If common electrodes are connected to common electrode lines through via holes periodically, then the resistance is decreased, but the space on the array substrate cannot be effectively utilized and the aperture ratio is reduced
Solution Approach 1:
The patent changes the connection method from vertical via holes to horizontal/in-plane connections. The common electrode is connected to the common electrode line through a connection electrode that extends in the plane of the substrate, utilizing the gate line as a reference boundary. This dimensional change eliminates the need for via holes while maintaining electrical connection, thereby increasing the aperture ratio without compromising conductivity.
Solution Approach 2:
The patent extracts and eliminates the via hole structure from the conventional design. By removing the via holes that connect common electrodes to common electrode lines, the patent eliminates the space occupation and light leakage issues associated with via holes, while maintaining the essential function of electrical connection through alternative in-plane connection paths.
2Reliability
If via holes are located within display area to connect source electrode to pixel electrode, then the connection is achieved, but light leakage occurs and aperture ratio is decreased
Solution Approach 1:
The patent removes via holes from the display area entirely. The connection between source electrode and pixel electrode is achieved through in-plane connection structures that extend along the gate line, eliminating the need for vertical via holes within the display area. This extraction of via holes prevents light leakage while maintaining electrical connectivity.
Solution Approach 2:
The patent introduces connection electrodes as intermediary structures that facilitate the electrical connection between source electrode and pixel electrode without requiring via holes. These connection electrodes extend in the plane of the substrate and connect to the gate line, serving as mediators that achieve the connection function while avoiding the harmful effects of via holes in the display area.
3Object-affected harmful factors
If black matrix is formed to shield via holes, then light leakage is prevented, but the irregular shape does not conform to the black matrix on color filter substrate, causing horizontal stripes
Solution Approach 1:
The patent extracts and eliminates via holes from the display area, thereby removing the root cause of the black matrix shape irregularity. Without via holes requiring shielding, the black matrix can be formed with uniform shapes that conform to the color filter substrate, eliminating the horizontal stripes caused by shape mismatches while still preventing light leakage.
Data Source
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AI summary
Embodiments of the invention disclose an array substrate, a liquid crystal display panel and a driving method for increasing aperture ratio of a pixel area, avoiding display horizontal stripes caused by difference in shape between black matrices in adjacent rows and improving display quality. The array substrate comprises: a plurality of data lines and a plurality of gate lines which are provided to intersect each other, and a plurality of pixel units, which are defined by enclosing by the plurality of data lines and the plurality of gate lines and are arranged in an array form, and each of which comprises a thin film transistor and a pixel electrode, the thin film transistor comprising a gate electrode, a source electrode connected to a corresponding data line and a drain electrode connected to the pixel electrode; two gate lines which are adjacent to each other are located between corresponding pixel units in two adjacent rows driven by the two gate lines, and for each of the pixel units in the two adjacent rows, a connection position of the drain electrode of the thin film transistor and the pixel electrode is between the two gate lines or over one corresponding gate line.