Array Substrate With Inclined Isolation Layer Protrusion
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Solution Overview
Problem
Existing array substrates have a large non-transmissive area occupied by thin film transistors and gate lines, which restricts the improvement of the aperture ratio due to the limitations in manufacturing processes, particularly in the width of the gate line and the U-shaped pattern of the active layer.
Innovation Solution
The array substrate design incorporates a protrusion portion in the isolation layer with inclined lateral surfaces, allowing the thin film transistors and gate lines to be arranged on these surfaces, reducing the non-transmissive area and increasing the aperture ratio by optimizing the arrangement of the active layer and gate line on the inclined surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin film transistors and gate lines are arranged on a flat substrate surface, then manufacturing process is simple, but the non-transmissive area is large which restricts aperture ratio improvement
Solution Approach 1:
The patent transitions from a two-dimensional flat substrate surface to a three-dimensional inclined surface structure. By forming the isolation layer with inclined lateral surfaces, the gate lines and thin film transistors are arranged on this inclined surface rather than on a flat plane. This dimensional change allows the electrical components to be positioned more efficiently, reducing their projection area on the substrate and thereby reducing the non-transmissive area while maintaining electrical functionality.
Solution Approach 2:
The patent applies local quality by creating a specific inclined surface structure only in the regions where gate lines and thin film transistors need to be arranged. The isolation layer is formed with inclined lateral surfaces specifically at these locations, while other regions of the substrate maintain their original flat structure. This localized structural modification optimizes the aperture ratio without requiring complete restructuring of the entire substrate.
2Area of stationary object
If gate line width is reduced to improve aperture ratio, then non-transmissive area decreases, but manufacturing precision requirements increase due to process limitations
Solution Approach 1:
By arranging gate lines on an inclined surface rather than a flat surface, the patent effectively reduces the projection width of gate lines when viewed from the display front. The inclined geometry allows the gate lines to maintain their electrical functionality while occupying less area in the transmissive region, thereby reducing the non-transmissive area without requiring extreme reduction in actual gate line dimensions that would demand excessive manufacturing precision.
3Reliability
If U-shaped active layer pattern is used for thin film transistor, then device functionality is achieved, but the pattern occupies significant non-transmissive area due to process constraints
Solution Approach 1:
The patent arranges the U-shaped active layer pattern on an inclined surface of the isolation layer. This three-dimensional arrangement allows the active layer to maintain its necessary U-shape for thin film transistor functionality while reducing its orthogonal projection area on the substrate. The inclined positioning enables more compact packaging of the active layer structure, thereby reducing the non-transmissive area occupied by the transistor components.
Data Source
AI summary
An array substrate and a fabrication method thereof, and a display panel are provided. The array substrate includes: a base substrate; an isolation layer on the base substrate; and a first thin film transistor on the isolation layer and a first gate line extending in a gate line direction, wherein the first thin film transistor includes a first gate electrode and a first active layer, the isolation layer includes a protrusion portion which extends in the gate line direction and protrudes upwards with respect to the base substrate, and each of orthogonal projections of the first active layer and the first gate electrode of the first thin film transistor on the main surface of the base substrate is overlapped with an orthogonal projection of the first lateral surface of the protrusion portion on the main surface of the base substrate.