Array Substrate Manufacturing via Transparent Insulating Layer
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Solution Overview
Problem
Conventional methods for manufacturing array substrates in TFT-LCDs require complex half-tone mask processes, increasing process difficulty and costs due to multiple patterning steps, which can lead to unstable performance of thin-film transistors.
Innovation Solution
A manufacturing method that eliminates the half-tone mask process by forming a pattern layer with an opening area greater than the gap between source and drain electrodes, allowing the pixel electrode to be electrically connected with the drain electrode, and includes a transparent organic insulating layer and adhesion layer to enhance bonding and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a half-tone mask process is applied to form semiconductor active layer and source/drain electrodes in one patterning process, then the number of patterning processes is reduced, but the process difficulty increases and TFT performance becomes unstable
Solution Approach 1:
The patent divides the patterning process into multiple independent steps: first forming the gate electrode pattern, then forming the semiconductor active layer pattern, and finally forming the source/drain electrode pattern. This segmentation allows each layer to be patterned separately with precise control, avoiding the performance instability caused by attempting to form multiple layers in a single half-tone mask process.
2Reliability
If at least one pattern layer with other specific function is arranged in the array substrate to optimize performances and increase flatness, then the array substrate performance is improved, but the number of patterning processes increases
Solution Approach 1:
The patent employs a transparent organic insulating layer that serves multiple functions simultaneously: it provides electrical insulation between the source/drain electrodes and the pixel electrode, enhances surface flatness for subsequent processing steps, and reduces parasitic capacitance. By combining these multiple functions into a single layer, the patent improves array substrate performance without proportionally increasing the number of patterning processes.
3Adaptability or versatility
If multiple patterning processes are performed including film forming, exposing, developing, etching and stripping for each pattern layer, then the pattern layers with specific functions are formed, but the process complexity and cost increase
Solution Approach 1:
The patent combines the formation of the transparent organic insulating layer with the formation of other pattern layers in the manufacturing process. By merging these steps and using the transparent organic insulating layer to serve multiple purposes, the patent reduces the overall number of separate patterning processes required, thereby simplifying the manufacturing process and reducing costs while still achieving the necessary pattern layer functionality.
Data Source
AI summary
A method for manufacturing an array substrate, comprising forming a pattern of a gate electrode by one pattering process; forming a gate insulating layer on a substrate provided with the pattern of the gate electrode; forming first and second patterns thereon, in which the first pattern corresponds to a pattern of a semiconductor active layer and the second pattern corresponds to a source electrode and a drain electrode; forming a pattern layer including an opening area on the substrate provided with the second pattern, in which the opening area corresponds to a gap between the source electrode and the drain electrode, the minimum width thereof being greater than the width of the gap between the source electrode and the drain electrode, and at least forming a pattern of the source electrode and the drain electrode and a pixel electrode electrically connected with the drain electrode through the opening area.