Array Substrate Interconnect Pad Layout for Radiation Detector Downsizing
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Solution Overview
Problem
The challenge is to downsize radiation detectors while avoiding interference between flexible printed circuit boards and ensuring adequate spacing for electronic components, which is hindered by the shortening of dimensions in the array substrate, leading to difficulties in interconnect operations and component arrangement.
Innovation Solution
The array substrate is designed with a substrate having sides extending in different directions, with control lines and data lines forming effective pixel regions subdivided into blocks, and strategically positioned interconnect pads that create longer distances between peripheral edge regions, reducing interference and facilitating easier interconnect operations and component arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the array substrate is made smaller to downsize the radiation detector, then the overall detector size is reduced, but the distance between interconnect pad regions becomes short causing interference between flexible printed circuit boards
Solution Approach 1:
The patent positions interconnect pads at diagonally opposite peripheral edges of the array substrate rather than adjacent edges. This spatial rearrangement in multiple dimensions maintains adequate distance between flexible printed circuit boards while achieving overall detector downsizing.
2Volume of moving object
If the array substrate is made smaller, then the detector size is reduced, but the distance between electronic components in the circuit board becomes too short making component arrangement difficult
Solution Approach 1:
By positioning interconnect pads at diagonally opposite edges, the patent creates sufficient space on the circuit board for electronic component arrangement while maintaining the downsized detector form factor.
3Reliability
If interconnect pads are positioned at peripheral edges for flexible printed circuit board connection, then electrical connection is achieved, but interference between flexible printed circuit boards occurs when substrate size is reduced
Solution Approach 1:
The patent uses asymmetric positioning of interconnect pads at diagonally opposite edges rather than symmetric placement at adjacent edges. This asymmetric arrangement naturally increases the distance between flexible printed circuit boards and eliminates interference while maintaining reliable electrical connections.
Data Source
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AI summary
An array substrate according to an embodiment is provided with: a substrate having a first side extending in a first direction, and a second side extending in a second direction intersecting with the first direction; a plurality of control lines provided on the substrate and each extending in the first direction; a plurality of data lines provided on the substrate and each extending in the second direction; a photoelectric converter provided in each of a plurality of areas defined by the control lines and the data lines; first areas provided in a peripheral area of the substrate adjacent to the second side, and in which a plurality of first wire pads electrically connected to the control lines are provided; and second areas provided in a peripheral area of the substrate adjacent to the first side, and in which a plurality of second wire pads electrically connected to the data lines are provided. The distance between the first side and the center line, extending in the first direction, of each first area is longer than the distance between the first side and the center line, extending in the first direction, of areas including the plurality of control lines electrically connected to the plurality of first wire pads provided in the first area, and/or the distance between the second side and the center line, extending in the second direction, of each second area is longer than the distance between the second side and the center line, extending in the second direction, of areas including the plurality of data line electrically connected to the plurality of second wire pads provided in the second area.