Array Substrate Laser Annealing Reduces Mask Operations
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Solution Overview
Problem
The manufacturing process of array substrates for liquid crystal display panels is complex and costly, requiring multiple mask-based operations, which hampers efficiency and increases costs, while also limiting the aperture ratio and performance of thin-film transistors.
Innovation Solution
A simplified manufacturing method involving a reduction metal layer and laser annealing to form source, drain, and pixel electrodes with reduced mask operations, using a combination of indium gallium zinc oxide (IGZO) and manganese or aluminum, and applying half-tone mask plates to pattern the metal and semiconductor layers, reducing the number of masks needed from five to six to at most three.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask-based operations are used to pattern metal and semiconductor layers, then the array substrate can be manufactured with conventional processes, but the manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent combines multiple patterning operations into a single mask-based operation. Specifically, it forms the gate electrode, source/drain electrodes, and pixel electrode patterns simultaneously in one masking step, eliminating the need for separate patterning operations for each electrode type. This merging of operations directly reduces manufacturing complexity while maintaining pattern accuracy and reliability.
Solution Approach 2:
The patent employs a universal patterning approach where a single mask pattern serves multiple functions: defining the gate electrode, source/drain electrodes, and pixel electrode patterns all in one operation. This multi-functional mask design eliminates the need for multiple specialized masks and operations, reducing both complexity and cost while ensuring consistent patterning quality across all electrode structures.
2Reliability
If multiple mask-based operations are used for patterning, then conventional manufacturing processes can be followed, but the manufacturing cost and time increase
Solution Approach 1:
The patent merges five to six separate mask-based patterning operations into a single masking operation. This consolidation dramatically reduces the number of manufacturing steps, decreases production time, and lowers costs while maintaining consistent patterning quality across all electrode structures through the unified mask design.
Solution Approach 2:
The patent performs preliminary patterning of all electrode structures (gate, source/drain, and pixel electrodes) in a single mask operation before subsequent processing steps. This preliminary action establishes all critical patterns simultaneously, eliminating the need for repeated masking operations and significantly improving manufacturing efficiency and productivity.
3Reliability
If conventional patterning methods are used, then manufacturing processes remain standard, but the aperture ratio and TFT performance are limited
Solution Approach 1:
The patent combines the patterning of gate, source/drain, and pixel electrodes into one operation, which enables precise control of the aperture ratio by optimizing the relative positioning of all electrode patterns simultaneously. This merged approach allows for better spatial coordination that maximizes the aperture area while maintaining proper electrode spacing and alignment, thereby improving aperture ratio precision and TFT performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces the number of mask-based operations, simplifies the manufacturing process, enhances the performance of thin-film transistors, and increases the aperture ratio of the array substrate, while maintaining high image quality and low power consumption.
Implementation Method 1
conductive patterns that have been reduced by laser annealing
Implementation Method 2
the source pattern, the drain pattern, and the pixel electrode pattern which are to be reduced, to conductors
Data Source
AI summary
The present invention provides an array substrate and a manufacturing method thereof. The method includes covering a reduction metal layer on an oxide semiconductor layer film and simultaneously forming a source pattern, a drain pattern, a pixel electrode pattern, and an oxide semiconductor layer through patterning the oxide semiconductor layer film and the reduction metal layer with one mask-based operation, followed by reducing the source pattern, the drain pattern, and the pixel electrode pattern to conductors through laser annealing to simultaneously form a source electrode, a drain electrode, and a pixel electrode. The entire manufacturing process needs, at most, only three rounds of mask-based operations so that, compared to the prior art, the number of mask-based operations required can be effectively reduced, the manufacturing operation can be simplified, and the performance of a TFT can be improved and an aperture ratio of the array substrate can be increased.