Array Substrate Layered Line Layout for High-Resolution Pixels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing array substrates in liquid crystal panels require significant spacing between conductive portions and signal electrode lines to avoid short circuits, limiting the ability to achieve high resolution due to the need for sufficient space between the conductive portions and drain electrodes.
Innovation Solution
The array substrate design includes a first line, a second line, and a first electrode with specific configurations and insulating films to allow for closer pixel arrangements, utilizing a novel configuration of conductive layers and connections to enable high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sufficient space is provided between the conductive portion and signal electrode line to avoid short circuit, then reliability is improved, but the pixel interval cannot be reduced and high resolution cannot be achieved
Solution Approach 1:
The gate electrode line is divided into segment parts arranged in different layers (first conductive film layer and second conductive film layer). The conductive portion connects these segment parts through contact holes in the insulating film, utilizing the third dimension (vertical layering) to reduce horizontal spacing requirements between pixels while maintaining adequate isolation to prevent short circuits.
2Reliability
If sufficient space is provided between the conductive portion and drain electrode to avoid short circuit, then reliability is improved, but the pixel interval cannot be reduced and high resolution cannot be achieved
Solution Approach 1:
The gate electrode line segments are positioned in different vertical layers, with the conductive portion connecting them through contact holes penetrating the insulating film. This vertical arrangement allows the drain electrode to be positioned closer to the pixel center while maintaining sufficient horizontal clearance from the gate electrode segments, enabling reduced pixel intervals without compromising short circuit prevention.
3Ease of manufacture
If the gate electrode line is made as a single continuous structure, then manufacturing is simpler, but the pixel interval cannot be reduced for high resolution
Solution Approach 1:
The gate electrode line is segmented into multiple parts (first gate electrode line segment and second gate electrode line segment) positioned in different layers. Each segment can be independently formed and positioned, allowing optimized spacing and routing that enables reduced pixel intervals while maintaining electrical continuity through the conductive portion connecting the segments via contact holes.
Data Source
AI summary
An array substrate includes a first line extending along a first direction, a second line extending along a second direction that crosses the first direction, a first electrode, and a first insulating film. The first line includes a first line section and a second line section each of which is a portion of a first conductive film, and a first connection electrode that is a portion of a second conductive film. Each of the second line and the first electrode is a portion of the second conductive film. The first line section includes a first end portion. The second line section includes a second end portion that is away from the first end portion in the second direction and is between the second line and the first electrode in the first direction. The first connection electrode extends from the first end portion to the second end portion.