Array Substrate Lead Plating for Uniform Thickness and Low Voltage Drop
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Solution Overview
Problem
Existing methods for manufacturing metal leads in array substrates, such as those used in Micro LED and Mini LED display panels, face challenges in controlling the morphology and thickness uniformity, leading to non-uniform voltage distribution and insufficient driving current for light-emitting devices.
Innovation Solution
A method involving the formation of a conductive seed layer, a removable pattern-defining layer, and a metal plating layer using electroplating or chemical plating processes, followed by removal of the pattern-defining layer and excess seed layer, to create a first lead layer with precise control over morphology and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a thick copper metal lead is manufactured directly on the base substrate by copper electroplating, then the voltage drop across the metal lead is reduced, but the application scope is greatly limited and the morphology and thickness uniformity cannot be precisely controlled
Solution Approach 1:
The patent divides the metal lead formation process into multiple stages: first forming a conductive seed layer with uniform thickness, then using a removable pattern-defining layer to create lead openings, and finally performing electroplating only in the exposed regions. This segmentation allows precise control over the morphology and thickness of the metal lead while maintaining low voltage drop through controlled thick copper deposition.
Solution Approach 2:
The patent performs preliminary actions by first forming a uniform conductive seed layer across the entire base substrate before pattern definition. The removable pattern-defining layer is then formed to prepare for selective electroplating. This preliminary uniform layer formation ensures that subsequent electroplating occurs on a consistent base, achieving both uniformity and precise morphological control.
2Loss of energy
If a seed lead is formed on the base substrate followed by copper electroplating to create a thick metal lead, then the voltage drop is reduced, but the method is difficult to precisely control the morphology and thickness uniformity
Solution Approach 1:
The patent introduces a removable pattern-defining layer as an intermediary element between the conductive seed layer and the final metal lead structure. This intermediary layer enables precise pattern definition and controls the electroplating process, allowing thick copper deposition only where needed while maintaining uniform thickness and morphology. The intermediary layer is later removed to complete the process.
3Ease of manufacture
If conventional electroplating is used to form metal leads, then the process is simple, but the thickness uniformity and morphology control are insufficient
Solution Approach 1:
The patent applies local quality by forming the conductive seed layer with uniform thickness across the entire base substrate first, then using the removable pattern-defining layer to create localized lead openings. The electroplating process is confined to these specific local regions, ensuring that copper deposition occurs uniformly only where required. This localized approach maintains process simplicity while achieving excellent thickness uniformity and morphology control in the final metal lead structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures uniformity and sufficient driving current to light-emitting devices, overcoming limitations of previous methods by achieving consistent metal lead formation and reducing voltage drops.
Implementation Method 1
forming, in the lead opening, a metal plating layer on the surface of the conductive seed layer by using an electroplating process or a chemical plating process
Implementation Method 2
forming, in the lead opening, a metal plating layer on the surface of the conductive seed layer by using an electroplating process or a chemical plating process
Data Source
AI summary
A method for manufacturing an array substrate and an array substrate are provided. The method includes: providing a base substrate; forming a driving circuit layer at a side of the base substrate; and forming a functional device layer at a side of the driving circuit layer. Forming the driving circuit layer includes forming at least one first lead layer. Forming the first lead layer includes: forming a conductive seed layer at the side of the base substrate; forming a removable pattern-defining layer on a surface of the conductive seed layer, the removable pattern-defining layer being provided with a lead opening exposing a part of the conductive seed layer; forming, in the lead opening, a metal plating layer on the surface of the conductive seed layer; removing the removable pattern-defining layer; and removing a part of the conductive seed layer not covered by the metal plating layer.