Array Substrate Lead-Line Encapsulation for Narrow-Bezel Displays
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Solution Overview
Problem
Existing display technologies face challenges in reducing the frame width of display panels due to the exposure of lead lines connecting signal lines and driving circuits, which are prone to erosion from the external environment.
Innovation Solution
The array substrate design includes a base substrate with a display area divided into regular and bonding sub-areas, featuring thin film transistors, bonding pads, and lead lines that are unexposed and encapsulated by insulating layers, preventing exposure and erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lead lines are exposed to connect signal lines and driving circuits, then electrical connection is achieved, but the lead lines are prone to erosion from external environment
Solution Approach 1:
The patent applies this principle by using insulating layers (including planarization layers and encapsulation layers) that form thin film structures covering and protecting the lead lines. These insulating layers act as protective shells that prevent direct contact between the lead lines and external environment, thereby preventing erosion while maintaining electrical connections.
Solution Approach 2:
The patent applies this principle by introducing insulating layers as intermediary substances between the lead lines and the external environment. These insulating layers serve as mediators that allow the lead lines to function electrically while preventing harmful interactions with air and water vapor, thus resolving the contradiction between exposure for connection and protection from erosion.
2Reliability
If lead lines are encapsulated by insulating layers to prevent erosion, then reliability is improved, but frame width increases
Solution Approach 1:
The patent uses thin film insulating layers that provide protective encapsulation with minimal thickness. The planarization layers and encapsulation layers are designed as thin films that protect the lead lines without adding significant width to the frame, thus maintaining narrow frame width while providing erosion protection.
Solution Approach 2:
The patent protects lead lines by extending protection in the vertical dimension (through multiple stacked insulating layers) rather than increasing horizontal dimension (frame width). The encapsulation is achieved through z-direction layering (base substrate, planarization layers, encapsulation layers) rather than x-y plane expansion, allowing protection without frame width increase.
3Reliability
If multiple insulating layers are added to encapsulate lead lines, then protection effectiveness increases, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the insulating layers: the planarization layers simultaneously provide surface flattening and partial insulation, while the encapsulation layers provide both electrical insulation and environmental protection. This merging of functions reduces the need for separate protective structures, simplifying the overall manufacturing process despite multiple layers.
Solution Approach 2:
The insulating layers are designed to perform multiple functions: electrical insulation, environmental protection, surface planarization, and structural support. This multi-functionality means that the same layers provide multiple benefits, reducing the need for additional specialized components and processes, thereby managing manufacturing complexity while achieving comprehensive protection.
Data Source
AI summary
An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.