Array Substrate Layout for Gate-Line Overlap Leakage Control
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Solution Overview
Problem
Existing OLED display technologies face issues with transistor leakage and inefficient light emission control due to overlapping projections of gate lines and node connecting lines, leading to inconsistent brightness and reduced display performance.
Innovation Solution
The array substrate design incorporates a non-overlapping layout of gate lines and node connecting lines, along with a compensating transistor and voltage supply network, to prevent transistor leakage and ensure consistent light emission by maintaining a stable driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If gate lines and node connecting lines are arranged in overlapping projections, then the display area can be increased, but transistor leakage occurs and light emission control becomes inconsistent
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional planar arrangement to a three-dimensional stacked arrangement. The gate line is positioned in a first plane while the node connecting line is positioned in a second plane at a different height, allowing their projections to overlap on the substrate without physical intersection. This vertical separation eliminates parasitic capacitance and prevents transistor leakage while maintaining high display area utilization.
2Productivity
If gate lines and node connecting lines are arranged in overlapping projections, then the pixel density can be increased, but brightness consistency deteriorates
Solution Approach 1:
By arranging the gate line and node connecting line in different vertical planes, the patent eliminates parasitic capacitance that would otherwise cause inconsistent light emission control. This ensures that each pixel receives accurate driving signals, maintaining brightness consistency across the display while enabling higher pixel density through overlapping projections.
3Reliability
If gate lines and node connecting lines are arranged in different planes, then transistor leakage is prevented, but device complexity increases
Solution Approach 1:
The patent divides the conductor layer into multiple segments at different vertical levels. The gate line resides in a first conductor layer while the node connecting line resides in a second conductor layer at a different height. This segmentation allows the lines to occupy the same horizontal projection area without electrical interference, preventing transistor leakage while managing complexity through modular layer construction.
Data Source
AI summary
An array substrate includes a plurality of pixel driving circuits and a plurality of gate lines. A respective pixel driving circuit includes a driving transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connecting line. A respective gate line is configured to provide gate scanning signal to the data write transistor in the respective pixel driving circuit. A gate electrode of the driving transistor is connected to the third capacitor electrode. The first node connecting line connects a second electrode of the first reset transistor with the third capacitor electrode. An orthographic projection of the respective gate line on a base substrate is substantially non-overlapping with an orthographic projection of the first node connecting line on the base substrate.