Array Substrate Leakage Current Reduction via Oxide Sidewall Barrier
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Solution Overview
Problem
Conventional low temperature poly-silicon (LTPS) display technologies face high production costs and uneven brightness due to excimer laser annealing, and leakage current issues in bottom-gated structures, limiting the production of large-sized display panels.
Innovation Solution
An array substrate is designed with an oxide layer on the sidewalls of the active and crystallization layers to prevent contact between the source/drain metal layer and the active layer, reducing leakage current paths by forming a through hole and using a passivation layer to cover the source/drain metal layer, which includes molybdenum and aluminum-copper layers, and a polysilicon-boron crystallization layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excimer laser annealing (ELA) technology is adopted for crystallization, then high electron mobility and large on/off states current ratio are achieved, but production cost increases and uneven brightness occurs
Solution Approach 1:
The patent changes the crystallization method from excimer laser annealing to solid phase crystallization with boron ion implantation, modifying the physical and chemical parameters of the process to achieve cost reduction while maintaining electron mobility through optimized doping and thermal treatment parameters
2Reliability
If excimer laser annealing (ELA) technology is adopted for crystallization, then high electron mobility is achieved, but crystallization uniformity deteriorates causing uneven brightness
Solution Approach 1:
The patent modifies the crystallization process parameters by using solid phase crystallization with controlled boron ion implantation and thermal annealing, achieving uniform crystallization throughout the active layer while maintaining high electron mobility through optimized temperature and time parameters
3Device complexity
If bottom-gated structure is used, then device fabrication is simplified, but leakage current increases due to contact between source/drain metal layer and amorphous silicon
Solution Approach 1:
The patent segments the active layer into distinct functional regions including a crystallization layer and an amorphous silicon layer, with the source/drain metal layer contacting only the crystallized region through precisely positioned contact holes, thereby separating the conduction path from the amorphous silicon that causes leakage
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the source/drain metal layer and the amorphous silicon layer, preventing direct contact and the associated leakage current while allowing the metal layer to maintain electrical contact with the crystallized active layer through controlled contact holes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces leakage current and enhances crystallization uniformity, enabling the production of large-sized display panels with improved brightness and reduced production costs.
Implementation Method 1
forming an oxide layer on sidewalls of the active layer and the crystallization layer, the oxide layer is used to obstruct the source/drain metal layer from contacting the active layer
Implementation Method 2
in which implanting a certain amount of boron ions before crystallization can greatly reduce the temperature and time required for crystallization
Implementation Method 3
rapidly heating the amorphous silicon material to crystallize a crystallization layer
Data Source
AI summary
The present disclosure provides an array substrate and a method of preparing the same. The array substrate includes a substrate, a gate, a gate insulation layer, an active layer, a crystallization layer, an oxide layer, a source/drain metal layer, and a passivation layer. After the crystallization layer is prepared, a mask plate is not removed and is used to protect an upper surface of the crystallization layer from oxidation reaction. Then, an oxide layer is formed on sidewalls of the crystallization layer and the active layer. The oxide layer is used to obstruct the source/drain metal layer from contacting the active layer. The source/drain metal layer is only in contact with the crystallization layer, thereby reducing a path of leakage current and achieving a purpose of reducing the leakage current.