Array Substrate Light-Blocking Layout for Signal Reliability
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Solution Overview
Problem
The reliability of signal transmission in array substrates is compromised due to light leakage caused by the generation of optical carriers in the active layer, leading to issues like light leakage, deteriorated vertical crosstalk, and threshold voltage offset.
Innovation Solution
An array substrate design featuring a gate insulation layer and an active layer with a light blocking layer in the peripheral region, where the light blocking layer has a higher surface height than the active layer, preventing light from entering the active region and reducing diffuse reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate insulation layer is extended to the peripheral region without additional light blocking structures, then the manufacturing process is simpler, but light leakage occurs due to diffuse reflection in the peripheral region causing optical carrier generation in the active layer
Solution Approach 1:
The gate insulation layer is segmented into a central region and a peripheral region. The central region is overlapped with the active layer for normal transistor operation, while the peripheral region is surrounded by the light blocking layer to prevent light leakage. This segmentation allows different functional zones within the gate insulation layer to address both manufacturing simplicity and signal reliability.
Solution Approach 2:
The light blocking layer acts as an intermediary structure between the gate insulation layer and the active layer in the peripheral region. It blocks light from entering the active layer through the gate insulation layer, preventing optical carrier generation and signal leakage, while maintaining the simplicity of the gate insulation layer structure.
2Device complexity
If no light blocking layer is added, then the device structure is simpler, but light enters the active region through diffuse reflection causing optical carrier generation and threshold voltage offset
Solution Approach 1:
The light blocking layer converts the potentially harmful diffuse reflection of light in the peripheral region into a beneficial light-blocking function. By strategically placing the light blocking layer around the peripheral region, the structure that could have caused light leakage is transformed into an effective light-shielding barrier, preventing optical carrier generation while maintaining reasonable structural complexity.
3Ease of manufacture
If the light blocking layer height is less than the active layer height, then the manufacturing process is easier, but light can still enter the active layer through the top surface causing signal leakage
Solution Approach 1:
The light blocking layer extends in the vertical dimension (height direction) beyond the active layer surface. This dimensional extension ensures that light is blocked not only at the lateral boundaries but also from above, preventing optical carriers from being generated in the active layer while maintaining manufacturing feasibility through standard thin-film deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents light leakage and optical carrier generation in the active layer, enhancing signal reliability and reducing crosstalk and threshold voltage offset.
Implementation Method 1
the light blocking layer is configured to be disposed in the peripheral region of the gate insulation layer to shield the light incident into the peripheral region, thereby preventing the light from being further incident into the active region due to diffuse reflection in the peripheral region
Data Source
AI summary
The present application provides an array substrate including at least a gate layer, a gate insulation layer, an active layer, and a light blocking layer, wherein the gate insulation layer and the active layer are disposed sequentially on the gate layer, the gate insulation layer has a central region overlapped with the active layer and a peripheral region surrounding the central region, the active layer has a first surface away from the gate insulation layer, and the gate insulation layer has a third surface located in the central region and in contact with the active layer, and the light blocking layer is disposed in the peripheral region and having a second surface away from the gate insulation layer, wherein a height of the second surface relative to the third surface is greater than a height of the first surface relative to the third surface.


