Array Substrate Light Shielding Metal Portions Parasitic Capacitance

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Solution Overview

Problem

In liquid crystal display devices, parasitic capacitance between gate lines and data lines interferes with display quality, and existing manufacturing processes for top-gate LTPS LCD array substrates are complex due to the need for precise doping and mask processes.

Innovation Solution

The array substrate design includes light shielding metal portions between gate lines and the base substrate, dividing gate lines into sub-segments connected in series through these metal portions, which increases the distance between gate lines and data lines, reducing parasitic capacitance and simplifying the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If gate lines and data lines are disposed close to each other in conventional TFT-LCD, then the device area is minimized, but parasitic capacitance between gate lines and data lines increases interfering with display quality

Engineering Contradiction:
Improveparasitic capacitanceVSAvoiddevice area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The gate line is divided into multiple gate line sub-segments that are separated by the data line. Each gate line sub-segment is independently connected to the gate electrode, creating discrete sections rather than a continuous gate line. This segmentation reduces the overlapping area between gate lines and data lines, thereby minimizing parasitic capacitance while maintaining functional integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The light shielding metal portion is positioned in a different layer (between the base substrate and the gate lines) rather than in the same plane as the gate and data lines. This vertical stacking in another dimension allows the gate lines and data lines to be disposed close together horizontally while the light shielding metal portion provides electrical isolation and shielding in the vertical dimension, reducing parasitic capacitance without increasing device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If complex doping and mask processes are used for precise gate line formation, then manufacturing precision is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvegate line formation precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The light shielding metal portion serves multiple functions simultaneously: it shields the liquid crystal from light leakage, acts as an electrical connection between adjacent gate line sub-segments, and provides structural support. By merging these functions into a single component, the manufacturing process is simplified as fewer separate steps are needed compared to conventional methods requiring separate doping and mask processes for precise gate line formation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The light shielding metal portion automatically provides electrical connection between gate line sub-segments through its inherent conductivity and physical positioning, eliminating the need for additional connection structures or complex alignment processes. The component serves itself by providing both optical shielding and electrical connectivity functions without requiring separate manufacturing steps.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11448929B2Array substrate with light shielding metal portions and manufacturing method thereof, display device
Publication Date: 2022.09.20 BEIJING BOE TECH DEV CO LTD
  • US11448929B2 patent drawing
  • US11448929B2 patent drawing
  • US11448929B2 patent drawing

AI summary

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.