Array Substrate Layout for LTPS-Oxide TFT Process Simplification
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Solution Overview
Problem
The manufacturing process of array substrates comprising low temperature polysilicon thin film transistors and oxide thin film transistors is complicated, and the electrical characteristics of oxide thin film transistors are affected by high-temperature processes, leading to performance degradation.
Innovation Solution
The array substrate design includes low temperature polysilicon thin film transistors and oxide thin film transistors with the gate electrode, source electrode, and drain electrode in the same layer, while the active layer and oxide semiconductor layer are in different layers, allowing for shared photomasks and simplified manufacturing, and the oxide semiconductor layer is protected from doping and high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If low temperature polysilicon thin film transistors and oxide thin film transistors are fabricated in the same manufacturing process with active layers and oxide semiconductor layers on the same layer, then the number of photomasks is reduced, but the electrical characteristics of oxide thin film transistors are affected by high-temperature laser annealing processes
Solution Approach 1:
The patent applies layer separation by moving the oxide semiconductor layer to a different layer (either above or below the active layer) rather than keeping them on the same layer. This dimensional reorganization allows both transistor types to coexist in the same device without their active layers interfering with each other during high-temperature processing, thus resolving the contradiction between manufacturing simplicity and electrical stability.
Solution Approach 2:
The patent extracts the oxide semiconductor layer from the same layer as the active layer and places it in a separate layer. This extraction protects the oxide semiconductor layer from the harmful effects of high-temperature laser annealing processes used for the low temperature polysilicon active layer, maintaining its electrical characteristics while still allowing integration in the same device.
2Ease of manufacture
If oxide semiconductor layers are exposed to high temperature processes, then manufacturing is simplified, but additional carriers are induced in the oxide semiconductor layers causing threshold voltage changes
Solution Approach 1:
By relocating the oxide semiconductor layer to a different layer position (above or below the active layer), the patent creates a physical barrier that protects the oxide semiconductor from high-temperature laser annealing. This spatial separation maintains manufacturing simplicity while preventing threshold voltage drift caused by thermal exposure.
Solution Approach 2:
The patent uses the active layer and its associated gate structure as an intermediary barrier between the high-temperature processing zone and the oxide semiconductor layer. This intermediary protects the temperature-sensitive oxide semiconductor from direct thermal exposure during manufacturing.
Data Source
AI summary
An array substrate includes at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor. The low temperature polysilicon thin film transistor includes an active layer and a first gate electrode. The oxide thin film transistor includes an oxide semiconductor layer, a second source electrode, and a second drain electrode. The first gate electrode, the second source electrode, and the second drain electrode are disposed in a same layer, and the active layer and the oxide semiconductor layer are disposed in different layers. A method is used for fabricating the array substrate. A display panel includes the array substrate.