Array Substrate Manufacturing for ADSDS LCD Brightness
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Solution Overview
Problem
Conventional exposure apparatus limitations restrict the formation of strip electrodes with widths less than 3 μm, leading to defects like mura or spots and decreased display quality in ADSDS LCD panels, while smaller pitch electrodes improve brightness but narrow the process window for uniformity.
Innovation Solution
A manufacturing method for an array substrate involving the formation of a gate electrode, common electrode, gate insulating layer, source/drain layer, passivation layer, and pixel electrode, with specific etching and ashing processes to achieve strip electrodes with a pitch of 4.5-6 μm, width of 1.5-2 μm, and spacing of 3-4 μm, enhancing brightness and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the pitch of strip electrodes is reduced to improve brightness, then transmittance increases, but the process window for maintaining uniform brightness becomes narrower
Solution Approach 1:
The patent applies parameter changes by modifying the electrode dimensions: reducing pitch from conventional values to 4.5-6 μm, reducing width to 1.5-2 μm, and adjusting spacing to 3-4 μm. These parameter changes enable smaller pitch electrodes that improve brightness while the precise control of these parameters maintains manufacturing feasibility and uniformity.
2Illumination intensity
If the width of strip electrode is reduced to less than 3 μm to improve brightness, then transmittance increases, but conventional exposure apparatus cannot achieve such small widths
Solution Approach 1:
The patent changes the dimensional parameters to achieve widths of 1.5-2 μm, which are smaller than the conventional 3-5.0 μm exposure limit. This parameter change enables improved brightness while the multi-step etching process provides the manufacturing capability to achieve these small dimensions that conventional single-step exposure cannot produce.
Solution Approach 2:
The patent segments the electrode formation process into multiple etching steps (first etching, ashing, second etching) rather than using a single exposure and etching step. This segmentation enables precise control of the electrode width at 1.5-2 μm, overcoming the limitation of conventional exposure apparatus while achieving the desired small dimensions for improved brightness.
3Illumination intensity
If the pitch of strip electrode is reduced to improve brightness, then transmittance increases, but defects like mura or spots occur due to width variation
Solution Approach 1:
The patent changes the pitch parameter to 4.5-6 μm, which is smaller than conventional pitches, thereby improving brightness and transmittance. Simultaneously, the precise control of electrode width (1.5-2 μm) and spacing (3-4 μm) through the multi-step etching process minimizes width variation, preventing defects like mura or spots and maintaining high display quality.
Solution Approach 2:
The patent segments the etching process into multiple controlled steps (first etching, ashing, second etching) to achieve precise width control at 1.5-2 μm. This segmented approach reduces width variation compared to single-step processes, thereby preventing display defects while enabling the smaller pitch necessary for improved brightness and transmittance.
Data Source
AI summary
The present disclosure relates to an array substrate and the manufacturing method thereof, and a display apparatus. The manufacturing method of the array substrate comprises following step. A gate insulating layer and an active layer is formed on the substrate with said gate electrode and said common electrode formed thereon. A source drain layer is formed on the substrate with said gate insulating layer and said active layer formed thereon. A passivation layer is formed on the substrate with said source drain layer formed thereon, and a through hole is formed in the passivation layer; a pixel electrode is formed on the substrate with said passivation layer formed thereon with said through hole. The pixel electrode is connected to the drain electrode in the source drain layer through said through hole. The process for forming the pixel electrode comprises first etching, ashing and second etching.