Array Substrate Mask Reduction via Indium Particle Seeded Crystallization
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Solution Overview
Problem
The existing methods for fabricating array substrates with different types of transistors in display and frame regions require separate masks for each process, increasing production costs and complexity.
Innovation Solution
A method is developed to divide the array substrate into regions with oxide thin film transistors in one area and microcrystalline silicon thin film transistors in another, using a shared mask process to form both types of transistors by converting indium oxide thin films into indium particles and forming microcrystalline silicon semiconductor layers, allowing for the fabrication of both types of transistors using the same mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate masks are used for fabricating oxide thin film transistors and microcrystalline silicon thin film transistors, then the performance requirements of each transistor type are met, but the production cost and process complexity increase
Solution Approach 1:
The substrate is divided into a first region for oxide thin film transistors and a second region for microcrystalline silicon thin film transistors. The buffer layer is selectively removed in the second region to expose the substrate, allowing different transistor types to be fabricated in different regions using the same mask pattern.
Solution Approach 2:
A buffer layer is formed on the entire substrate before transistor fabrication. This buffer layer is then selectively removed in the second region before forming the semiconductor layers, preparing the substrate for microcrystalline silicon transistor fabrication while preserving the buffer layer for oxide transistor fabrication in the first region.
2Manufacturing precision
If separate masks are used for each transistor type, then each transistor type can be precisely fabricated, but the number of production steps and costs increase
Solution Approach 1:
A single mask pattern is designed to serve both oxide thin film transistor fabrication in the first region and microcrystalline silicon thin film transistor fabrication in the second region. The same mask is used for patterning both transistor types, eliminating the need for separate masks and reducing production steps.
Solution Approach 2:
The buffer layer is selectively removed only in the second region where microcrystalline silicon transistors are to be fabricated, while the buffer layer is retained in the first region for oxide transistor fabrication. This local differentiation allows both transistor types to be fabricated with the same mask while maintaining their specific performance requirements.
3Device complexity
If the same mask is used for both transistor types, then the number of masks and process complexity are reduced, but the different performance requirements of each transistor type must be satisfied
Solution Approach 1:
The buffer layer is selectively removed only in the second region where microcrystalline silicon transistors are to be fabricated, while the buffer layer is retained in the first region for oxide transistor fabrication. This local differentiation allows both transistor types to be fabricated with the same mask while maintaining their specific performance requirements.
Solution Approach 2:
The substrate is divided into a first region for oxide thin film transistors and a second region for microcrystalline silicon thin film transistors. The buffer layer is selectively removed in the second region to expose the substrate, allowing different transistor types to be fabricated in different regions using the same mask pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of masks required and simplifies the process, lowering production costs while meeting the distinct performance needs of each transistor type.
Implementation Method 1
performing a reduction process on the second indium oxide thin film to obtain indium particles
Implementation Method 2
inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles
Implementation Method 3
inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles
Implementation Method 4
performing the reduction process on the second indium oxide thin film via hydrogen plasma
Data Source
AI summary
The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.