Array Substrate Metal Capacitor Plates for LTPS Charging Speed

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Solution Overview

Problem

The manufacturing process of array substrates for LTPS TFTs is complex and costly, with the charging speed of storing capacitors being affected due to the use of doping methods, which reduces the competitive advantage of LTPS TFT array substrates, especially in high-resolution display panels.

Innovation Solution

The array substrate design includes a thin film transistor and a storing capacitor with both plates formed of metal material, where the dielectric layer is made of the same material as the gate insulation layer, allowing for simplified patterning processes and improved charging speed, reducing the number of patterning processes and ion injection steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If doping method is used to form the first plate of the storing capacitor, then the manufacturing process can be completed, but the charging speed of the storing capacitor becomes slow

Engineering Contradiction:
Improvecharging speed of storing capacitorVSAvoidmanufacturing process complexity
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The patent changes the material parameter of the first plate from doped semiconductor to metal material. This parameter change fundamentally improves the electrical conductivity and charging speed of the storing capacitor, while the metal material can be deposited using standard sputtering or evaporation techniques, maintaining manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the ion injection method (physical doping process) with a metal deposition process. This substitution eliminates the complex ion injection equipment and process control requirements, simplifying the manufacturing system while achieving faster charging performance

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If eight patterning processes with eight masks are used to manufacture the array substrate, then the storing capacitor and thin film transistor can be formed with correct patterns, but the manufacturing complexity and cost increase

Engineering Contradiction:
Improvepattern formation accuracyVSAvoidnumber of patterning processes
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the formation of the first plate of the storing capacitor with the formation of the source and drain electrodes into a single patterning process. Both structures are patterned simultaneously using the same mask and deposition process, reducing the total number of patterning steps from eight to fewer steps while maintaining precise pattern alignment

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes the first plate of the storing capacitor serve multiple functions: it acts as both the capacitor electrode and part of the conductive structure that connects to the source/drain region. This multi-functionality reduces the need for separate dedicated capacitor electrode patterning steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the charging speed of the storing capacitor and simplifies the manufacturing process, leading to improved display quality and reduced production costs, ensuring high-resolution display capabilities.

Implementation Method 1

the storing capacitor comprises a first plate, a second plate and a dielectric layer provided between the first plate and the second plate, wherein both of the first plate and the second plate are formed of metal material

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9524991B2Array substrate and manufacturing method thereof and display apparatus
Publication Date: 2016.12.20 BOE TECHNOLOGY GROUP CO LTD
  • US9524991B2 patent drawing
  • US9524991B2 patent drawing
  • US9524991B2 patent drawing

AI summary

An array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate are provided. The array substrate comprises a base substrate, and a thin film transistor and a storing capacitor provided on the base substrate, the thin film transistor comprises a gate, a source, a drain and a gate insulation layer provided between the source and drain and the gate, the storing capacitor comprises a first plate, a second plate and a dielectric layer provided between the first plate and the second plate, wherein, both of the first plate and the second plate are formed of metal material, and the dielectric layer is formed of the same material as the gate insulation layer. In the array substrate of the present invention, the charging speed of the storing capacitor can be improved and the display quality of the display apparatus comprising the array substrate is further improved.