Array Substrate Metal-Layer Layout to Reduce TFT Leakage
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Solution Overview
Problem
Thin film transistors in array substrates are prone to leakage when the display panel is cut, leading to abnormal images due to the formation of flat capacitors between the thin film transistor, frame starting signal line, and gate driving circuit structure, which disrupts the normal functioning of the gate driving circuit.
Innovation Solution
The array substrate design includes a first metal layer partially overlapping with a second metal layer on an insulating layer, reducing the facing area between the thin film transistor and the gate driving circuit, and incorporating multiple staggered metal electrodes to minimize leakage by increasing the transmission path and reducing the risk of electrical leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a thin film transistor is arranged between the frame starting signal line and the gate driving circuit structure to enable cut-screen functionality, then the gate driving circuit can be triggered after cutting, but the thin film transistor becomes prone to leakage due to the formation of a flat capacitor at the connection point
Solution Approach 1:
The patent extracts the problematic flat capacitor structure by separating the metal layers with an insulating layer. The first metal layer (from thin film transistor) and second metal layer (from gate driving circuit) are taken out and positioned on opposite sides of the insulating layer, eliminating the direct capacitive coupling that causes leakage while maintaining electrical connection through laser fusion.
Solution Approach 2:
The insulating layer acts as an intermediary between the first metal layer and second metal layer. It provides physical separation to prevent direct capacitive coupling (reducing leakage) while still allowing laser fusion to create conductive pathways for signal transmission, thus mediating between the need for electrical connection and the need to prevent leakage.
2Ease of operation
If the metal layers are directly connected to ensure signal transmission, then the gate driving circuit functions normally, but the facing area between metal layers creates a flat capacitor that causes leakage
Solution Approach 1:
The patent transitions from a two-dimensional direct contact arrangement to a three-dimensional staggered arrangement with an insulating layer in between. The first metal layer and second metal layer are positioned at different heights and lateral positions, creating a multi-dimensional structure that reduces overlapping area and capacitive coupling while maintaining signal transmission through controlled fusion points.
3Reliability
If the thin film transistor connection area is increased to improve connection reliability, then signal transmission is enhanced, but the leakage risk increases due to larger facing area forming a bigger flat capacitor
Solution Approach 1:
The connection structure is segmented into distinct first metal layer and second metal layer portions positioned on opposite sides of the insulating layer. This segmentation allows the connection area to be distributed across multiple smaller fusion points rather than one large overlapping area, maintaining connection reliability while reducing the capacitive coupling area that causes leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the risk of leakage and ensures normal operation of the gate driving circuit, maintaining image quality by minimizing electrical contact between the thin film transistor and the gate driving circuit, even when the display panel is cut.
Implementation Method 1
there is a flat capacitor at the connecting among the thin film transistor, the frame starting signal line and the gate driving circuit structure
Data Source
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AI summary
Disclosed are are an array substrate,a display panel and a display. The array substrate is provided with a thin film transistor (T) and a gate driving circuit (G). A trigger signal input terminal of the gate driving circuit (G) corresponds to an output terminal of the thin film transistor (T), a first insulating layer (30) is provided between a first metal layer (10) corresponding to the output terminal of the thin film transistor (T) and a second metal layer (20) corresponding to the trigger signal input terminal of the gate driving circuit (G). A projected area of the first metal layer (10) on the first insulating layer (30) is partially overlapped with a projected area of the second metal layer (20) on the first insulating layer (30), which reduces the positive area between the first metal layer (10) of the thin film transistor (T) and the second metal layer(20) of the gate driving circuit (G) and can effectively avoid the leakage condition of the thin film transistor.