Array Substrate Motherboard ESD Protection via Conductive Connection Lines
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Solution Overview
Problem
The accumulation of static electricity during the manufacturing process of display panel motherboards can lead to electrostatic discharge (ESD), causing damage such as burned protective circuits and short circuits, which affects the quality and reliability of the display panels.
Innovation Solution
The implementation of an array substrate motherboard with connection lines that electrically connect array substrates together, allowing static electricity to be dispersed and reducing the risk of ESD by providing a path for electrostatic charges to flow and be discharged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If array substrates are handled manually during manufacturing operations, then operational flexibility is maintained, but static electricity accumulates and causes ESD damage
Solution Approach 1:
The patent utilizes the harmful static electricity charges and converts them into a beneficial effect by connecting all array substrates through conductive patterns to form a common electrostatic potential. This allows accumulated static charges to be safely distributed and discharged through the connection lines to the ground, preventing ESD damage while maintaining manual handling operations.
2Reliability
If connection lines are added to electrically connect array substrates, then static electricity dispersion is improved, but device complexity increases
Solution Approach 1:
The patent merges the ESD protection function with the existing conductive patterns on the array substrates. The connection lines are integrated into the substrate structure itself, sharing the same conductive material layers and manufacturing processes, thereby providing ESD protection without adding separate complex structures.
Solution Approach 2:
The conductive patterns serve multiple functions: they provide electrical connections for normal display operation and simultaneously serve as ESD protection paths. The same connection lines that carry display signals also function as static electricity discharge paths, eliminating the need for dedicated ESD protection structures.
3Reliability
If multiple connection lines are used to connect all array substrates, then static electricity discharge capability is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent creates an equipotential network by connecting all array substrates through conductive patterns to a common ground potential. This equipotential structure allows static electricity to naturally flow from any substrate to ground through the connection lines, providing effective ESD protection with a simple and uniform manufacturing approach that can be implemented using standard thin-film deposition and patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the accumulation of static electricity, preventing damage to the display panels and improving product yield by ensuring that static electricity is dissipated across the connected substrates, thereby enhancing the reliability of the manufacturing process.
Implementation Method 1
The plurality of connection lines are electrically connected to first conductive terminals of electrical test regions of the plurality of array substrates to electrically connect the plurality of array substrates together
Implementation Method 2
If an amount of the accumulated static electricity is excessive, an electro-static discharge (ESD) will cause great damage to a display panel
Data Source
AI summary
An array substrate motherboard includes a plurality of array substrates and a plurality of connection lines. Each of the plurality of array substrates includes an electrical test region, and the electrical test region includes a first conductive terminal. The plurality of connection lines are electrically connected to first conductive terminals of electrical test regions of the plurality of array substrates to electrically connect the plurality of array substrates together.