Array Substrate Motherboard Testing via Planar Bridge Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The electro-static discharge phenomenon at via holes in bridge circuits during testing of gate lines in TFT-LCDs can lead to breakdown of gate lines and abnormal lighting issues, which existing technologies have not adequately addressed.
Innovation Solution
The array substrate motherboard design includes gate line and data line testing leads and pads made of the same material and in the same layer, eliminating the need for via holes and reducing the risk of electro-static discharge, with additional dummy pads and insulating layers to enhance testing and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate lines and testing lines are connected through bridge circuits with via holes, then testing signals can be transmitted to gate lines, but electro-static discharge occurs at the via holes causing gate line breakdown and abnormal lighting
Solution Approach 1:
The patent removes the via holes from the connection path between testing lines and gate lines. By extracting the problematic via hole component, the design eliminates the electro-static discharge issue while maintaining the testing functionality through direct planar connections.
Solution Approach 2:
The patent transitions from a three-dimensional via hole connection (vertical dimension) to a two-dimensional planar connection (horizontal dimension). The testing lines connect to gate lines through bridge circuits on the same layer, eliminating the need for vertical via holes and their associated electro-static discharge risks.
2Measurement precision
If multiple block pins correspond to multiple lead regions for testing, then comprehensive testing coverage is achieved, but the complexity of the testing mechanism increases
Solution Approach 1:
The patent creates a universal testing mechanism where a standardized bridge circuit pattern can be reused across multiple lead regions. Each block pin follows the same connection methodology through bridge circuits, allowing comprehensive testing coverage without proportionally increasing mechanism complexity.
Solution Approach 2:
The patent divides the testing mechanism into independent, modular bridge circuits for each lead region. Each segment can be independently configured and tested, allowing comprehensive coverage while maintaining manageable complexity through modular design.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~3
AI summary
In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.