Array Substrate Multi-Gate Transistor Bias Stress Reduction
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Solution Overview
Problem
State-of-the-art metal oxide thin-film transistors suffer from performance instability due to negative bias stress, leading to abnormal display phenomena when the gate is under a low voltage level for an extended time, causing a negative shift in the transistor threshold voltage.
Innovation Solution
The array substrate design incorporates multiple switching transistors connected to different gate lines, allowing all transistors to be turned on concurrently during a pixel electrode charging period with an effective voltage level, and turned off using a second voltage level outside this period, balancing the ON and OFF states to reduce bias stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate of the metal oxide thin-film transistor is kept at a low voltage level for a relatively long time, then the transistor can maintain its switching function, but the transistor threshold voltage level shifts negatively due to negative bias stress
Solution Approach 1:
The patent applies periodic action by implementing a dual-gate control mechanism where gate lines are alternately switched between high and low voltage levels in a periodic manner. This prevents any single gate from being continuously subjected to negative bias stress, thereby maintaining transistor threshold voltage stability while preserving switching functionality.
Solution Approach 2:
The patent changes the voltage level parameter of the gate lines dynamically. By switching between high voltage level (turning on transistors) and low voltage level (turning off transistors) in a controlled periodic sequence, the system prevents continuous negative bias stress accumulation, thus resolving the threshold voltage shift issue.
2Reliability
If multiple switching transistors are used with different gate lines, then the pixel electrode can be charged only when all transistors are turned on concurrently, but the control complexity increases
Solution Approach 1:
The patent segments the control of switching transistors by assigning each transistor to a different gate line. This segmentation allows independent control of each transistor through its dedicated gate line, enabling precise timing control where all transistors must be simultaneously turned on for pixel electrode charging, thereby ensuring display reliability.
Solution Approach 2:
The patent implements multi-functionality by using multiple gate lines that serve dual purposes: individually controlling specific switching transistors and collectively enabling pixel electrode charging when all are activated. This universal control mechanism achieves both precise transistor control and reliable image display without proportionally increasing complexity.
Data Source
AI summary
The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines.