Array Substrate Etching via Multi-Layer Conductive Segmentation
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Solution Overview
Problem
The existing manufacturing methods for array substrates in TFT-LCDs result in a size difference between the first electrode and the gate, which limits the aperture ratio of the display panel due to inefficient etching processes and the use of multiple mask plates.
Innovation Solution
A manufacturing method that involves depositing a first electrode layer with at least two conductive layers having different etching rates, using a halftone mask plate to expose and develop a photoresist layer, and performing sequential etching processes to reduce the width difference between the first electrode and the gate, thereby increasing the etching speed and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-layer first electrode layer is used with conventional etching, then the manufacturing process is simple, but the etching speed is slow and the width difference between first electrode and gate is large
Solution Approach 1:
The first electrode layer is divided into multiple conductive layers with different etching rates. This segmentation allows each layer to be etched at different speeds, with the faster-etched lower layer creating a stepped structure that accelerates overall etching while the slower upper layer maintains precise width control, reducing the width difference between electrode and gate.
Solution Approach 2:
Different conductive layers are assigned different local qualities in terms of etching rate. The lower conductive layer has a higher etching rate to quickly remove material and create the stepped structure, while the upper conductive layer has a lower etching rate to maintain precise dimensional control and reduce width difference with the gate.
2Manufacturing precision
If multiple mask plates are used to form first electrode and gate separately, then manufacturing precision is improved, but device complexity and process time increase
Solution Approach 1:
The formation of the first electrode and gate is merged into a single masking and etching process. By using a multi-layer conductive structure with different etching rates, both patterns are simultaneously formed from one mask, eliminating the need for separate mask plates and reducing process complexity while maintaining precision through the stepped etching mechanism.
Solution Approach 2:
The etching rate parameter is changed across different conductive layers. This parameter variation allows a single etching process to differentially etch each layer, enabling simultaneous formation of precise electrode and gate patterns from one mask while controlling the width difference through the inherent etching rate differences of the materials.
3Productivity
If the first electrode width is made larger than gate width, then manufacturing is easier, but the aperture ratio of display panel is reduced
Solution Approach 1:
The etching process becomes dynamic through the stepped structure. As etching progresses, the lower conductive layer is removed faster, creating a stepped profile where the etching solution accesses the upper layer at different positions. This dynamic process automatically reduces the width difference between electrode and gate during etching, enabling better aperture ratio without sacrificing manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the etching speed of the first electrode layer, reduces the size difference between the first electrode and the gate, and increases the aperture ratio of the display device, leading to improved display performance.
Implementation Method 1
exposing and developing the photoresist layer using a halftone mask plate
Implementation Method 2
performing a first etching process on the gate metal layer; etching the first electrode layer
Implementation Method 3
ashing the photoresist layer
Data Source
Figure 1a~1d
Figure 2~3a
Figure 3b~3e
AI summary
The present disclosure relates to a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method comprises sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates; forming a photoresist layer on the gate metal layer; exposing and developing the photoresist layer using a halftone mask plate; performing a first etching process on the gate metal layer; etching the first electrode layer; ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.