Array Substrate Multiplexing Layout for Narrow OLED Bezels
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Solution Overview
Problem
Existing OLED display panel designs face challenges in optimizing the layout of multiplexing circuits, leading to potential interference and increased space occupation, which affects the reduction of frame size and process complexity.
Innovation Solution
The array substrate design incorporates a multiplexing circuit with switch transistors sharing electrodes and a specific layout of connecting lines that avoid overlapping with multiplexing units, reducing interference and optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the multiplexing circuit is arranged close to the display area to reduce frame size, then the occupied space is reduced, but the wiring may overlap with other circuits causing interference
Solution Approach 1:
The patent applies dimensional change by routing control signal lines through the corner area (peripheral area) rather than through the display area, and by stacking conductive layers vertically. This allows the multiplexing circuit to be positioned close to the display area for compactness while avoiding overlap with data lines and other circuits in the display region, thus reducing interference.
Solution Approach 2:
The patent segments the array substrate into distinct functional regions: display area, peripheral area, and corner area. The multiplexing circuit is placed in the corner area while data lines are confined to the display area. This spatial segmentation prevents wiring overlap and reduces interference between different circuit types while maintaining a compact overall structure.
2Adaptability or versatility
If multiple data lines are connected to the multiplexing unit, then the multiplexing function is enhanced, but the wiring complexity and space occupation increase
Solution Approach 1:
The multiplexing unit is designed with a universal structure that can connect to multiple data lines through a shared electrode configuration. The switch transistors share common first and second electrodes, allowing a single multiplexing unit to control multiple data lines efficiently. This multi-functional design enhances adaptability while keeping the wiring structure relatively simple and organized within the corner area.
3Area of stationary object
If the multiplexing unit shares electrodes with switch transistors, then space is saved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent merges the electrode structures of the multiplexing unit and switch transistors by sharing common first and second electrodes. This consolidation reduces the total number of electrodes and simplifies the overall structure, saving space. The shared electrode design also provides mutual electrical connection and control functionality, enhancing the integration level of the circuit.
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
Provided are an array substrate and a display device. The array substrate includes: a base substrate including a display area and a peripheral area surrounding the display area, and including a first peripheral area located on one side of the display area; a plurality of sub-pixels and data lines located at the display area; a plurality of control signal lines, data signal input lines and a multiplexing circuit located at least at the first peripheral area. At least one multiplexing unit includes a plurality of switch transistors, at least one of which including: a first active layer located on one side of the base substrate, a first gate including a first gate portion and a second gate portion spaced apart and electrically connected to a control signal line; two first electrodes electrically connected to the first active layer and a data signal input line; and a second electrode electrically connected to the first active layer and one of at least two data lines, an orthographic projection of the second electrode on the base substrate being located between orthographic projections of the two first electrodes on the base substrate.