Array Substrate Via Layout for Mura Reduction in Full-Screen Displays
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Solution Overview
Problem
Large-size full screen display products face image quality issues such as Mura (uneven brightness) due to existing array substrate designs.
Innovation Solution
The array substrate design includes a first base with pixel units, scanning lines, data lines, and common lines, featuring a via hole structure that connects scanning lines and reduces coupling capacitance, thereby addressing Mura issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scanning lines are arranged in conventional designs, then the array substrate can be manufactured, but coupling capacitance increases causing Mura (uneven brightness) problems
Solution Approach 1:
The scanning line structure is segmented into multiple independent scanning line groups, where each group contains multiple scanning lines that are spatially separated and independently routed. This segmentation reduces the coupling capacitance between adjacent scanning lines by increasing the distance between them and preventing direct electromagnetic interaction, thereby eliminating the Mura effect while maintaining comprehensive pixel coverage.
Solution Approach 2:
The patent transitions from a conventional two-dimensional scanning line arrangement to a three-dimensional routing structure by introducing via holes that connect scanning lines across different layers. This dimensional change allows scanning lines to be routed in different spatial planes, reducing parasitic coupling capacitance while maintaining electrical connectivity to all pixel units.
2Area of stationary object
If the array substrate uses full-screen design, then the display area is maximized, but image quality problems such as Mura occur
Solution Approach 1:
The display area is segmented into multiple scanning line groups with independent routing paths. Each group covers a specific region of the display area, allowing the entire full-screen area to be utilized while maintaining image quality through reduced coupling capacitance in each segmented region.
Solution Approach 2:
Via hole structures serve as intermediaries that connect scanning lines across different layers and regions. These intermediary connection points enable the scanning lines to reach all pixel units across the full display area while maintaining controlled impedance and minimizing parasitic effects that would otherwise degrade image quality.
3Object-generated harmful factors
If via hole structure is used to connect scanning lines, then coupling capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The via hole structures are merged with the existing multi-layer substrate manufacturing process. The via holes are formed as part of the standard layer stacking and patterning sequence, utilizing the same etching and filling processes already established for creating other conductive interconnections in the display device.
Solution Approach 2:
The via hole structures serve multiple functions simultaneously: they provide electrical connection between scanning lines on different layers, act as spacing elements to reduce coupling capacitance, and serve as alignment references for subsequent patterning steps. This multi-functionality reduces the need for additional specialized manufacturing steps.
Data Source
AI summary
An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.