Array Substrate Narrow Bezel Lead Wire Spacing
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Solution Overview
Problem
The existing manufacturing process for TFT-LCD array substrates faces challenges in reducing the spacing between lead wires in narrow bezel displays, leading to an increased probability of short-circuit defects due to the limitations of using a mask with a semipermeable membrane, which results in exposed semi-conductor active layers and reduced data line widths.
Innovation Solution
The implementation of an array substrate with criss-cross gate lines and data lines in the display area and first and second short-circuiting rings in the non-display area, where the first data lead wires are formed in the same layer as the gate lines and the second data lead wires are formed in the same layer as the data lines, allowing for interleaving and reducing the spacing between adjacent lead wires while avoiding short-circuit defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a mask with a semipermeable membrane is used to form data lines and lead wires in a single patterning process, then the manufacturing process is simplified and resistance between lead wires and data lines is reduced, but the spacing between adjacent lead wires cannot be sufficiently reduced leading to increased short-circuit defect probability
Solution Approach 1:
The lead wire structure is segmented into two separate layers: first lead wires formed in the gate metal layer and second lead wires formed in the source-drain metal layer. This segmentation allows independent optimization of each layer's pitch and positioning, enabling reduced spacing while maintaining manufacturing simplicity through separate patterning processes.
Solution Approach 2:
The invention transitions from a single-layer lead wire structure to a two-layer stacked structure, utilizing the vertical dimension to separate first lead wires and second lead wires. This dimensional change enables reduced horizontal spacing between adjacent lead wires while preventing short-circuit defects through layer isolation.
2Area of stationary object
If lead wires are wired in small space to meet narrow bezel requirements, then the display device achieves narrow bezel design, but adjacent lead wires become too close increasing short-circuit defect probability
Solution Approach 1:
By stacking first lead wires in the gate metal layer and second lead wires in the source-drain metal layer vertically, the invention reduces the horizontal spacing between adjacent lead wires in the non-display area, enabling narrow bezel design while preventing short-circuit defects through vertical separation.
3Manufacturing precision
If photoresist with larger thickness is used, then the photoresist can be ashed out at its edge to reduce data line width, but the semi-conductor active layer at the edge will be exposed increasing the risk of short-circuit defects
Solution Approach 1:
The patterning process is segmented into separate steps for data lines and lead wires, with the lead wire patterning performed after data line formation. This allows the use of thick photoresist for precise data line width control without exposing the semi-conductor active layer, as the lead wire etching occurs subsequently when the active layer is already protected.
Data Source
AI summary
The present invention provides an arrayed substrate, a method for manufacturing the same and a display device. It relates to a field of display technology. The short-circuit defect between the lead wires may be avoided while reducing a spacing between the adjacent two lead lines in a limited space for wiring. The array substrate comprises a plurality of criss-cross gate lines and data lines within a display area, and the array substrate further comprises a first short-circuiting ring and a second short-circuiting ring within a non-display area, and first data lead wires and second data lead wires connected electrically with the first short-circuiting ring and the second short-circuiting ring respectively; the first data lead wires are provided in the same layer and made from the same material as the gate lines for connecting electrically the first short-circuiting ring with first data lines of the data lines; the second data lead wires are provided in the same layer and made from the same material as the data lines for connecting electrically the second short-circuiting ring with second data lines of the data lines; wherein the first data lines are interleaved with the second data lines.