Array Substrate Non-Display Area Width Reduction via Layer Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face challenges in reducing the width of the non-display area without affecting performance or element sizes at the border, which limits the achievement of a narrow border design for large screen outdoor displays.
Innovation Solution
The arrangement of data signal fanout wires and the test switch assembly at different layers in the non-display area of the array substrate, allowing them to overlap, reduces the width of the non-display area without impacting performance or element sizes, thereby facilitating a narrow border design without increasing fabrication demands or degrading yield ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the sizes of elements at the border are reduced to achieve narrow border design, then the border width is reduced, but the fabrication process becomes more demanding and yield is affected
Solution Approach 1:
The patent introduces a multi-layer structure where data signal fanout wires are arranged at different layers from the test switch assembly. This vertical stacking approach allows elements to overlap in the plane view while being separated in the vertical dimension, reducing the horizontal border width without requiring smaller element sizes, thus avoiding fabrication complexity increases
2Length of stationary object
If the sizes of elements at the border are reduced to achieve narrow border design, then the border width is reduced, but the performance and element sizes at the lower border are affected
Solution Approach 1:
By arranging data signal fanout wires and test switch assembly at different layers, the patent enables these elements to occupy the same horizontal space without interfering with each other's dimensions. This allows the border width to be reduced while maintaining the original sizes and performance characteristics of individual elements
Solution Approach 2:
The patent implements a nested arrangement where data signal fanout wires at one layer are positioned to overlap with the test switch assembly at another layer. This nesting approach allows both elements to coexist in the same horizontal footprint, effectively reducing the border width while preserving element integrity
Data Source
AI summary
The disclosure discloses an array substrate, a display panel, and a display device, and the array substrate includes: a plurality of data lines arranged in a display area, and a demultiplexer assembly, a test switch assembly, and a plurality of data signal fanout wires, arranged respectively in a non-display area, where each of the signal output terminals of the demultiplexer assembly is electrically connected with one of the plurality of data lines, each of the signal input terminals of the demultiplexer assembly is electrically connected respectively with one of the plurality of data signal fanout wires, and one of the output terminals of the test switch assembly; and the test switch assembly is arranged on the side of the demultiplexer assembly away from the display area.