Array Substrate Bonding Pin Structure to Prevent Over-Etching
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Solution Overview
Problem
Existing array substrates face issues with metal sub-layers being partially exposed during the etching process, leading to over-etching and conductivity problems, which affect signal transmission uniformity.
Innovation Solution
The array substrate features a stacked structure of metal sub-layers in the bonding pins, where each sub-layer is either completely unexposed or encapsulated by another sub-layer or an insulating layer, ensuring complete coverage and preventing exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal sub-layers are partially exposed during the etching process, then the etching process can be completed, but over-etching occurs and conductivity problems arise
Solution Approach 1:
The patent implements a nested structure where multiple metal sub-layers (first, second, third metal sub-layers) are stacked within the bonding pin region. Each metal sub-layer is partially overlapped by the layer above it, creating a nested configuration. This nested arrangement ensures that when one metal sub-layer is etched, the underlying metal sub-layers remain as backup conductive paths, preventing complete conductivity loss and eliminating over-etching damage.
2Reliability
If metal sub-layers are completely covered by insulating layers, then conductivity is protected, but signal transmission capability is reduced
Solution Approach 1:
The patent applies local quality by differentiating the coverage of metal sub-layers with insulating layers in different regions. In the bonding pin region, metal sub-layers are partially exposed to maintain conductivity. In the pixel electrode region, the same metal sub-layers are completely covered by insulating layers to prevent signal leakage and ensure proper signal transmission. This localized differentiation of insulating layer coverage optimizes both conductivity protection and signal transmission.
Data Source
AI summary
An array substrate is provided. The array substrate includes a plurality of bonding pins in a bonding pin area. A respective bonding pin of the plurality of bonding pins is a stacked structure comprising N number of metal sub-layers sequentially arranged on a base substrate, a first metal sub-layer of the N number of metal sub-layers being on a side of an N-th metal sub-layer of the N number of metal sub-layers closer to the base substrate, the N-th metal sub-layer being a last metal sub-layer of the respective bonding pin, N is an integer≥2. In a first cross-section along a plane perpendicular to the base substrate, parallel to at least one of two lateral sides, and intersecting the N number of metal sub-layers of the respective bonding pin, any of the first metal sub-layer to an (N−1)-th metal sub-layer of the respective bonding pin are completely unexposed.