Array Substrate With Overlapping Fan-Out Traces For Narrow Bezel
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Solution Overview
Problem
Conventional LCD array substrates have a large bezel size due to extensive layout space occupied by fan-out traces, which hinders the implementation of narrow bezel panel displays.
Innovation Solution
The array substrate design incorporates partially overlapping first and second fan-out traces formed by different metal layers, with an insulating layer in between, and strategically positions bonding terminals to reduce the layout area and bezel width by utilizing both sides of the display area for fan-out trace connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fan-out traces are distributed on left and right sides of display area using same metal layer, then electrical connections are established, but layout space is occupied and bezel size increases
Solution Approach 1:
The patent transitions fan-out traces from a single-plane (2D) layout to a multi-layer (3D) structure by utilizing different metal layers. First fan-out traces are formed in a first metal layer while second fan-out traces are formed in a second metal layer, allowing traces to overlap in the planar view while maintaining electrical isolation through vertical separation. This dimensional change reduces the layout area occupied by fan-out traces without compromising electrical connection reliability.
Solution Approach 2:
The patent implements nesting by placing second fan-out traces within the projection area of first fan-out traces through multi-layer stacking. The second fan-out traces in the second metal layer are positioned to overlap with first fan-out traces in the first metal layer, creating a nested configuration that maximizes space utilization and reduces the overall bezel size while maintaining distinct electrical pathways.
2Length of moving object
If fan-out traces occupy large layout space, then electrical connections are maintained, but narrow bezel display cannot be implemented
Solution Approach 1:
By forming fan-out traces in multiple metal layers with vertical separation, the patent reduces the horizontal spread required for electrical connections. This allows the bonding terminals to be positioned closer to the display area, thereby reducing bezel width while maintaining manufacturing feasibility through standard multi-layer PCB fabrication processes.
Solution Approach 2:
The patent segments the fan-out trace system into multiple independent trace groups distributed across different metal layers. First fan-out traces in the first metal layer and second fan-out traces in the second metal layer can be independently routed and optimized, allowing for more efficient space utilization and reduced overall trace area while maintaining all necessary electrical connections.
Data Source
AI summary
An array substrate including a substrate, a plurality of fan-out traces and a plurality of bonding terminals. The substrate includes a display area and a non-display area surrounding the display area. The fan-out traces and the bonding terminals are disposed in the non-display area. The bonding terminals are spaced apart from each other. First ends of the fan-out traces are respectively electrically connected to the bonding terminals. Second ends of the fan-out traces are electrically connected to the display area. The fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces. The first fan-out traces are formed by a first metal layer. The second fan-out traces are formed by a second metal layer. An insulating layer is provided between the first metal layer and the second metal layer. The first fan-out traces and the second fan-out traces are partially overlapped.