Array Substrate Pad Stacking for LCD Panel Space Efficiency
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Solution Overview
Problem
As the resolution of LCD panels increases, the number of pads on the chip mounting area also increases, leading to a larger size of the LCD panel, necessitating a technique to enhance space utilization efficiency without expanding the panel size.
Innovation Solution
The array substrate incorporates a base substrate with input and output pad parts disposed at different layers within the chip mounting area, along with a pixel array and signal transmitting parts, allowing for a higher density of pads without increasing the panel size by utilizing space efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pads on the chip mounting area is increased to improve resolution, then the resolution is improved, but the size of the LCD panel increases
Solution Approach 1:
The patent applies dimensionality change by stacking pad parts in different layers (first pad part on the first substrate, second pad part on the second substrate) rather than arranging all pads in a single plane. This vertical stacking in the third dimension allows increasing the number of pads without expanding the horizontal area of the chip mounting region, thereby improving resolution while maintaining compact panel size.
Solution Approach 2:
The patent implements nesting by placing the second pad part on the second substrate within the same chip mounting area where the first pad part is located on the first substrate. The pad structures are nested vertically within the same horizontal footprint, allowing dense packing of pads without increasing the overall panel dimensions.
2Quantity of substance
If the chip mounting area size is increased to accommodate more pads, then the number of pads increases, but the total size of the LCD panel increases
Solution Approach 1:
The invention transitions from two-dimensional pad arrangement to three-dimensional stacking by placing pad parts on different substrates at different vertical levels. This enables accommodating a larger quantity of pads within the same chip mounting area footprint, increasing pad density without expanding the horizontal area.
Solution Approach 2:
The patent merges the function of multiple pad parts (first pad part and second pad part) into a single integrated chip mounting area. By combining vertical stacking with horizontal integration, the system achieves high pad quantity within a compact mounting region.
Data Source
AI summary
An array substrate includes a base substrate, an input pad part, a first output part, a second output pad part, a pixel array, and a signal transmitting part. The input pad part and the first output pad part are disposed at the chip mounting area of the base substrate. The second output pad part is also disposed at the chip mounting area, but disposed within a layer different from the first output pad part. The pixel array is disposed at an array area of the array substrate. The signal transmitting part is disposed at a signal transmitting area of the array substrate. Therefore, the first and second output pad parts are disposed at different layers, respectively, so that a space utilizing efficiency of the array substrate is enhanced.