Array Substrate PAD Region Scratch Resistance via Parallel Insulated Wiring
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Solution Overview
Problem
The existing array substrates face a high risk of scratches during the cutting process, leading to defective products due to the thickness of metal lines and bulges on the surface, which cannot be restored, thereby affecting the yield rate and display performance.
Innovation Solution
Incorporating conductive gate-line and data-line wirings parallel to the metal lines in the PAD regions, which are electrically insulated, to reduce the step and provide a means for restoring scratched lines, thus enhancing the substrate's resistance to scratches without compromising display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of metal film is reduced to reduce the step, then the ability of resisting scratch is improved, but the resistance and capacitance delay increase, worsening display performance
Solution Approach 1:
The patent divides the metal line structure into multiple segments: the original metal line and additional parallel metal lines. This segmentation allows the system to maintain adequate thickness for low resistance while distributing the signal transmission function across multiple conductors, thereby reducing the step height issue and scratch risk without compromising display performance
Solution Approach 2:
The patent introduces parallel metal lines in the same plane (another dimension) rather than simply reducing the thickness of the existing line. By adding conductors side-by-side, the solution addresses the scratch risk from a different dimensional approach while maintaining adequate cross-sectional area for low resistance and capacitance delay
2Object-affected harmful factors
If the thickness of metal film is reduced to reduce the step, then the ability of resisting scratch is improved, but defects such as residual image worsen and productivity decreases
Solution Approach 1:
The patent applies preliminary action by forming additional parallel metal lines during the manufacturing process before the cutting operation. This preventive measure ensures that even if scratching occurs during cutting, the signal can be restored or compensated through the parallel conductors, thereby maintaining high yield rate while addressing scratch risk
Solution Approach 2:
The patent implements a recovery mechanism where parallel metal lines serve as backup conductors. If scratching damages one line during cutting, the signal can be recovered through the remaining parallel lines, effectively discarding the damaged portion and recovering functionality, thus maintaining productivity and yield rate
Data Source
AI summary
The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.