Array Substrate Parasite Capacitance Reduction
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Solution Overview
Problem
Liquid crystal display (LCD) devices face challenges in reducing manufacturing costs and improving image display quality due to restricted pixel voltage differences and parasite capacitance between data lines, which affect the opening ratio and image display quality.
Innovation Solution
The design of an array substrate with specific configurations of gate and data lines, including the use of storage capacitors and alternating voltage applications, to maintain voltage differences and reduce parasite capacitance, enhancing the opening ratio and image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of gate and data lines is increased, then the display resolution is improved, but the opening ratio is decreased
Solution Approach 1:
The array substrate is divided into multiple scanning zones, with each zone having its own gate lines and switching elements. This segmentation allows independent control of different regions, enabling high resolution display while maintaining adequate opening ratios in each local area by optimizing line routing and reducing overall line count requirements.
Solution Approach 2:
The patent employs a 3-layer conductive structure with gate lines, data lines, and power lines arranged in different vertical layers. This spatial arrangement in multiple dimensions allows lines to cross without interference, reducing the need for additional lines and improving the opening ratio while maintaining high display resolution.
2Ease of manufacture
If the pixel voltage difference range is restricted, then the manufacturing cost is reduced, but the image display quality is deteriorated
Solution Approach 1:
The patent implements frame inversion driving where the polarity of voltage applied to pixel electrodes is alternated between frames. This parameter change allows the use of lower voltage magnitudes while maintaining image quality through cumulative effect over multiple frames, thereby reducing manufacturing costs without sacrificing display quality.
Solution Approach 2:
The patent employs periodic scanning of gate lines in a time-division multiplexing manner, where each gate line is activated sequentially rather than simultaneously. This periodic action reduces the voltage requirements and power consumption, lowering manufacturing costs while maintaining image display quality through the temporal integration of liquid crystal response.
3Device complexity
If parasite capacitance is formed between data lines, then the manufacturing complexity is reduced, but the image display quality is deteriorated
Solution Approach 1:
The patent extracts and separates data lines into different scanning zones and layers, physically removing the source of parasite capacitance between adjacent data lines. By routing data lines in different vertical layers and spacing them across different horizontal zones, the harmful capacitive coupling is eliminated while maintaining a relatively simple overall manufacturing process.
Solution Approach 2:
The patent introduces insulating layers and spacing structures as intermediary elements between data lines. These intermediaries prevent direct capacitive coupling while allowing the data lines to maintain their routing patterns, thus reducing parasite capacitance without significantly increasing manufacturing complexity.
Data Source
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AI summary
An array substrate (400) comprising a first pixel electrode (491a) overlapped with first and second power lines (431, 435) extended along a gate line (421), the first and second power lines (431, 435) being adapted to receive voltages having different polarities, respectively, the first pixel electrode (491a) being electrically connected to a first data line (471a; Dj); a second pixel electrode (491b) overlapped with the first and second power lines (431, 435), the second pixel electrode (491b; 591b) being electrically connected to a second data line (471b; Dj+1) being adapted to receive a voltage having an opposite polarity to a voltage applied to the first data line (471a; Dj); a first common electrode (491c) overlapping with the first and second power lines (431; 435), the first common electrode (491c) being electrically connected to the first power line (431); and a second common electrode (491d) overlapping with the first and second power lines (431; 435), the second common electrode (491d) being electrically connected to the second power line (435); wherein a capacitance (Cst) of the first common electrode (491c) with the second power line (435) is substantially the same as the sum of the capacitances of a capacitor (Csg) formed by overlapping the first pixel electrode (491a) and the first power line (431) and a capacitor (Csa) formed by overlapping the first pixel electrode (491a) and the second power line (435), and a capacitance (Cst) of the second common electrode (491d) with the first power line (431) is substantially the same as the sum of the capacitances of a capacitor (Csg) formed by overlapping the second pixel electrode (491b) and the first power line (431) and a capacitor (Csa) formed by overlapping the second pixel electrode(491b) and the second power line (435).