Array Substrate Layout for Lower Source-Line Parasitic Capacitance
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Solution Overview
Problem
In display devices with a thin film transistor of a bottom gate structure, the high resistance source section of the oxide semiconductor layer creates a large parasitic capacitance with other electrodes or lines, leading to a high load on the source line.
Innovation Solution
The array substrate includes a semiconductor section with a resistance lowered section that does not overlap the first electrode, and overlapping portions that overlap the first electrode and the second line, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the high resistance source section of the oxide semiconductor layer is connected to the source line without overlapping, then the结构简单性 is maintained, but the parasitic capacitance between the source section and other electrodes or lines becomes large, increasing the load on the source line
Solution Approach 1:
The semiconductor section is configured to extend in multiple directions, creating a first overlapping portion that overlaps both the gate electrode layer and the source line. This spatial arrangement in multiple dimensions allows the high resistance source section to have a smaller area while maintaining electrical connection, thereby reducing parasitic capacitance without complicating the overall structure
Solution Approach 2:
The semiconductor section has different resistance characteristics in different regions: a high resistance source section connected to the source line and a low resistance channel section under the gate electrode. By optimizing the local geometry of the high resistance source section to overlap both the gate electrode and source line, the parasitic capacitance is reduced while maintaining the necessary electrical properties
2Reliability
If the semiconductor section overlaps the gate electrode layer, then the transistor function is achieved, but the parasitic capacitance with the source line increases due to the high resistance source section
Solution Approach 1:
The semiconductor section is divided into functionally distinct regions: the channel section under the gate electrode layer that provides transistor functionality, and the high resistance source section that connects to the source line. The source section is further configured to have a first overlapping portion that overlaps both the gate electrode and source line, separating the transistor function from the parasitic capacitance issue
Solution Approach 2:
The high resistance source section is configured to extend not only under the gate electrode but also to overlap the source line, creating a three-dimensional spatial relationship that reduces the area of the high resistance source section. This dimensional optimization reduces parasitic capacitance while maintaining the necessary transistor function in the channel region
Data Source
AI summary
An array substrate includes a first line, a second line crossing the first line, a semiconductor section made of semiconductor material, extending to cross the first line, and including a first end portion overlapping the second line and a second end portion, a first insulation film between the first line and the semiconductor section, a first electrode being a portion of the first line and overlapping the semiconductor section via the first insulation film, a second electrode being a portion of the second line and overlapping the semiconductor section and being connected to the semiconductor section, and a third electrode disposed to overlap the second end portion of the semiconductor section and connected to the semiconductor section. The semiconductor section includes a resistance lowered section not overlapping the first electrode and a first overlapping portion overlapping a portion of the first electrode and a portion of the second line.