Array Substrate Parasitic Capacitance Reduction
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Solution Overview
Problem
The existing array substrates in display technology face challenges in reducing parasitic capacitance, which hinders the manufacturing of large-sized and high-resolution displays due to a large overlapping area between the source-drain and gate electrodes.
Innovation Solution
The array substrate design includes a substrate with a gate electrode, a gate insulation layer, a semiconductor active layer, a first etching barrier layer exposing both ends of the semiconductor active layer, and a source-drain layer covering these ends, reducing the overlapping area with the gate electrode and thereby minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source and drain electrodes are partially passed through the hole etched on the barrier layer to be overlapped with a central area of the semiconductor active layer, then the overlapping area between the source electrode and the drain electrode and the gate electrode under the semiconductor active layer is larger, but this causes a large parasitic capacitance of the thin film transistor
Solution Approach 1:
The patent extracts and removes portions of the etching barrier layer at both ends of the semiconductor active layer, creating exposed regions where the source and drain electrodes can be positioned without overlapping the gate electrode. This extraction of the barrier layer material enables the electrode configuration that reduces parasitic capacitance while maintaining proper electrical connections.
Solution Approach 2:
The patent changes the spatial arrangement of electrodes from a conventional overlapping configuration to a configuration where electrodes extend along the longitudinal direction of the semiconductor active layer. This dimensional repositioning reduces the overlapping area with the gate electrode in the vertical dimension while maintaining electrical functionality.
2Manufacturing precision
If the overlapping area between the source electrode and the drain electrode and the gate electrode is larger, then the parasitic capacitance is larger, but this makes large-sized and high-resolution display inconvenient to be manufactured
Solution Approach 1:
The patent extracts portions of the etching barrier layer to create exposed regions at both ends of the semiconductor active layer. This extraction enables precise positioning of source and drain electrodes that reduces overlapping with the gate electrode, thereby reducing parasitic capacitance and enabling high-resolution display manufacturing.
Solution Approach 2:
The patent applies different structural configurations to different regions: the etching barrier layer is removed at the ends of the semiconductor active layer while maintained in the central region. This local modification allows electrodes to be positioned optimally at the ends to reduce parasitic capacitance, while the central region maintains proper barrier functionality.
3Reliability
If the source and drain electrodes are positioned to overlap with the gate electrode under the semiconductor active layer, then the overlapping area is larger, but this increases parasitic capacitance and reduces display quality
Solution Approach 1:
The patent extracts portions of the etching barrier layer at both ends of the semiconductor active layer, creating exposed regions that allow source and drain electrodes to be positioned without overlapping the gate electrode. This extraction directly reduces parasitic capacitance and improves display quality.
Solution Approach 2:
The patent repositions electrodes to extend along the longitudinal direction of the semiconductor active layer rather than overlapping the gate electrode in the vertical dimension. This dimensional change reduces the overlapping area and parasitic capacitance while maintaining electrical connectivity.
Data Source
AI summary
An array substrate and a display panel; the array substrate includes a substrate (6), a gate electrode (2), a gate insulation layer (1), a semiconductor active layer, a first etching barrier layer (4), and a source-drain layer (5); the gate electrode (2) is disposed at the substrate (6); and the gate insulation layer (1) covers the gate electrode (2).