Array Substrate Passivation Layout Against Foreign-Matter Conduction
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Solution Overview
Problem
In the manufacturing of liquid crystal panels, foreign matter can easily be introduced between the array substrate and the cover plate, leading to abnormal display or failure of erasing handwriting due to conduction between the pixel electrode and the common electrode layer.
Innovation Solution
The array substrate includes a base substrate with a pixel electrode and a thin-film transistor in the display region, and a second passivation layer on the side facing away from the base substrate, which prevents foreign matter from conducting the pixel electrode and the common electrode layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single passivation layer is used between the pixel electrode and thin-film transistor, then the manufacturing process is simpler, but foreign matter can easily conduct the pixel electrode and common electrode layer causing display abnormalities
Solution Approach 1:
The single passivation layer is divided into two separate passivation layers (first passivation layer and second passivation layer) with different via structures. The first passivation layer has first vias for electrical connection, while the second passivation layer has second vias that are blocked or sealed. This segmentation provides both electrical connectivity where needed and foreign matter blocking where required, resolving the contradiction between manufacturing simplicity and display reliability.
2Manufacturing precision
If multiple separate mask plates are used for forming vias in different passivation layers, then the via formation precision is higher, but the manufacturing cost and process complexity increase
Solution Approach 1:
A single mask plate is designed to serve multiple functions: it defines the patterns for both first vias in the first passivation layer and second vias in the second passivation layer simultaneously. This universal mask plate achieves precise via formation for both layers while reducing the number of mask plates required, thereby lowering manufacturing complexity and cost while maintaining high via formation precision.
Data Source
AI summary
Provided is an array substrate. The array substrate us provided with a display region and a non-display region on a periphery of the display region, and includes: a base substrate; a pixel electrode and a thin-film transistor on a side of the base substrate, wherein the pixel electrode and the thin-film transistor are disposed in the display region, and the pixel electrode is disposed on a side, facing away from the base substrate, of the thin-film transistor; a first passivation layer between the pixel electrode and the thin-film transistor, wherein a plurality of first vias are defined in the first passivation layer; and a second passivation layer on a side, facing away from the base substrate, of the pixel electrode, wherein a plurality of second vias are defined in the second passivation layer.