Array Substrate Patterning Process Reduction
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Solution Overview
Problem
Current manufacturing methods for array substrates in liquid crystal displays require six times of patterning processes, which is inefficient and costly.
Innovation Solution
A reduced patterning process method for array substrates, involving forming a gate metal layer, semiconductor and source/drain metal layers, a first electrode, passivation, and organic insulating layers, and a second electrode in fewer steps, optimizing the structure and reducing the number of patterning processes from six to five.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If six times of patterning processes are used to form array substrate structure, then manufacturing precision and structural integrity are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple patterning operations into fewer steps by using a single mask plate to simultaneously define multiple structures. Specifically, the gate electrode, active layer, source/drain electrodes, and various insulating layers are formed through integrated patterning sequences that reduce the total number of separate patterning processes from six to fewer steps, while maintaining the required structural precision through careful process design
2Manufacturing precision
If six times of patterning processes are used to form array substrate structure, then structural integrity is improved, but productivity decreases
Solution Approach 1:
The patent combines multiple patterning steps into fewer operations by using a single mask plate that simultaneously patterns multiple features. This integration reduces the total process time and number of sequential steps required to achieve the same structural integrity, thereby improving manufacturing productivity and efficiency
3Productivity
If reduced patterning processes are used, then productivity and ease of manufacture are improved, but manufacturing precision may deteriorate
Solution Approach 1:
The mask plate serves multiple functions simultaneously - it defines the gate electrode, active layer, source/drain electrodes, and insulating layer patterns all in one or fewer patterning steps. This multi-functional approach maintains manufacturing precision by using a single patterning reference for all features, eliminating cumulative alignment errors that would occur with multiple separate patterning steps
Data Source
AI summary
A method for manufacturing the array substrate includes: forming a gate metal layer on a base by a first patterning process and forming a gate insulating layer on the gate metal layer; forming a semiconductor layer and a source/drain metal layer by a second patterning process on the resulted base, the source/drain metal layer including a data line and a metal electrode connected to the data line; forming a first electrode on the resulted base and forming a channel region by a third patterning process, the channel region causing the metal electrode to form a source electrode and a drain electrode; forming a passivation layer and an organic insulating layer by a fourth patterning process on the resulted base; the organic insulating layer at least corresponding to the data line; and forming a second electrode by a fifth patterning process on the resulted base.