Array Substrate Fabrication via Photoresist Edge Alignment
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Solution Overview
Problem
The existing methods for fabricating liquid crystal display (LCD) array substrates result in a large 'tail' of the active layer, leading to light leakage current, unstable pixel voltage, and flickering issues due to the isotropic nature of wet etching processes.
Innovation Solution
A method involving a substrate base layer with a gate electrode and insulating layer, followed by sequential formation of semiconductor and source-drain metal layers, using an island-like photoresist pattern for precise etching to align edges and reduce the active layer tail, incorporating amorphous silicon and doped layers, and optimizing etching conditions to minimize lateral etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used to form the source-drain metal layer, then the fabrication process is simple and efficient, but the lateral etching length becomes close to the vertical etching depth, causing the active layer to protrude and form a tail
Solution Approach 1:
The patent segments the etching process into two distinct stages: wet etching followed by dry etching. The wet etching stage removes the bulk of the source-drain metal layer, while the dry etching stage precisely controls the remaining material to achieve the desired thickness and eliminate the tail formation. This segmentation allows each etching method to perform its optimal function.
Solution Approach 2:
The patent introduces an intermediary layer (such as a buffer layer or sacrificial layer) between the source-drain metal layer and the active layer. This intermediary layer acts as a protective barrier during etching, preventing the etchant from reaching and damaging the active layer, thereby avoiding tail formation while allowing complete removal of the source-drain metal layer.
2Ease of manufacture
If the active layer extends beyond the source-drain metal layer, then the lithography process is straightforward, but light leakage current increases causing pixel voltage instability and display quality degradation
Solution Approach 1:
The patent performs preliminary action by extending the source-drain metal layer beyond the active layer boundaries before the final etching step. This over-extension ensures that after the two-stage etching process, the metal layer will precisely align with the active layer edges, preventing any active layer protrusion that would cause light leakage current and display defects.
Solution Approach 2:
The patent changes the etching parameters by transitioning from isotropic wet etching to anisotropic dry etching in the second stage. This parameter change allows precise control over the etching depth and lateral etching, enabling the source-drain metal layer to be etched to the exact required thickness without creating active layer tails, thereby eliminating light leakage current.
3Object-affected harmful factors
If the source-drain metal layer is etched to match the active layer length, then light leakage is reduced, but the etching process becomes more complex and time-consuming
Solution Approach 1:
The patent merges the source-drain metal layer formation with the active layer patterning process by using the same photoresist mask for both layers. This combined approach ensures automatic alignment between the metal layer and active layer, achieving precise length matching without requiring additional alignment steps, thereby maintaining high fabrication efficiency while reducing light leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the active layer tail, minimizing light leakage current and ensuring stable pixel voltages and improved display quality by aligning the semiconductor material layer edges with the source-drain metal layer edges.
Implementation Method 1
the source-drain metal layer is first wet etched by using the island-like photoresist pattern as a mask
Implementation Method 2
performing first dry etching for the semiconductor material layer by using the island-like photoresist pattern after first ashing as a mask
Data Source
AI summary
A method for fabricating an array substrate, after the wet etching process of the source-drain metal layer (17), performs first ashing for the island-like photoresist pattern (19), such that the edge of the island-like photoresist pattern (19) is aligned with the edge of the source-drain metal segment (171).