Array Substrate Etching via Photoresist Ashing to Reduce Leakage
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Solution Overview
Problem
The existing array substrates with active switches in display panels face high leakage current and poor stability due to the large edge extensions of semiconductor layers and doped layers, which increase power consumption and instability when irradiated by light.
Innovation Solution
A manufacturing method for array substrates that includes forming a patterned photoresist layer with specific thickness areas and performing photoresist ashing between wet and dry etching steps, controlling the etching rate ratio to reduce the excess length of the semiconductor and doped layers, thereby minimizing the leakage current and improving electrical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the semiconductor layer and doped layer are formed with conventional etching methods, then the active switch can be formed, but the edge extensions of the semiconductor layers are large, causing large leakage current and high power consumption
Solution Approach 1:
The patent changes the etching parameters by introducing a photoresist ashing step between wet and dry etching, controlling the lateral etching rate to be 0.05-0.15 microns while maintaining longitudinal etching rate at 0.5-1.5 microns. This parameter optimization reduces the over-etching effect that causes edge extensions, thereby reducing leakage current and power consumption while maintaining active switch functionality
Solution Approach 2:
The patent performs photoresist ashing as a preliminary action between wet and dry etching steps. This preliminary removal of photoresist material prevents excessive lateral etching of the semiconductor layers, ensuring that the edge extensions are minimized before the final dry etching step, thus reducing leakage current while maintaining the active switch structure
2Ease of manufacture
If the semiconductor layer and doped layer have large edge extensions, then the etching process is simpler, but the leakage current increases when light is irradiated, reducing stability
Solution Approach 1:
The patent optimizes etching parameters by controlling the lateral etching rate to 0.05-0.15 microns through photoresist ashing, balancing the simplicity of the etching process with the need to minimize edge extensions. This parameter control ensures that the active switch maintains high stability under light irradiation while the manufacturing process remains feasible
Solution Approach 2:
The patent introduces photoresist ashing as an intermediary step between wet and dry etching. This intermediary action removes excess photoresist material that would otherwise cause lateral over-etching, serving as a mediator that maintains both process simplicity and high active switch stability by controlling edge extensions
3Productivity
If conventional etching is used without photoresist ashing, then the manufacturing process is faster, but the lateral etching rate is too high, causing excess semiconductor layer length and increased leakage current
Solution Approach 1:
The patent changes the etching parameters by introducing photoresist ashing that controls the lateral etching rate to 0.05-0.15 microns. This parameter adjustment maintains reasonable manufacturing speed while significantly improving edge precision of the semiconductor layer, thereby reducing leakage current without excessive sacrifice of productivity
Solution Approach 2:
The patent performs photoresist ashing as a preliminary step before dry etching to remove excess photoresist material. This preliminary action prevents lateral over-etching, ensuring that the semiconductor layer edges are precisely defined before the final etching step, thus improving manufacturing precision while maintaining acceptable production speed
4Device complexity
If the photoresist layer is not ashed between etching steps, then the process is simpler and faster, but the excess length of semiconductor and doped layers increases, causing large leakage current
Solution Approach 1:
The patent changes the process parameters by introducing a photoresist ashing step that controls the lateral etching rate to 0.05-0.15 microns. This parameter change accepts increased device complexity in the form of an additional process step, but achieves the critical goal of minimizing excess semiconductor layer length and reducing leakage current
Solution Approach 2:
The patent performs photoresist ashing as a preliminary action between wet and dry etching steps. This preliminary removal of photoresist material prevents excessive lateral etching of the semiconductor and doped layers, ensuring that their edge extensions are minimized, thereby reducing leakage current despite the increased process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the leakage current and enhances the electrical stability of the active switches by minimizing the excess length of semiconductor and doped layers, leading to lower power consumption and improved performance.
Implementation Method 1
performing at least one wet etching on said source drain electrode layer to form a source electrode and a drain electrode of said active switch
Implementation Method 2
performing at least one dry etching on said semiconductor layer to form a channel area of said active switch
Implementation Method 3
performing at least one photoresist ashing between steps of said wet etching and said dry etching
Data Source
AI summary
The present disclosure discloses a manufacturing method for an array substrate and an array substrate. The method includes: forming a gate electrode, a gate insulating layer, a semiconductor layer, a source drain electrode layer and a photoresist layer on a substrate; patterning the photoresist layer to form a patterned photoresist layer; performing at least one wet etching on the source drain electrode layer and performing at least one dry etching on the semiconductor layer; performing an ashing processing between the steps of the wet etching and the dry etching. A ratio of a lateral etching rate to a longitudinal etching rate in the at least one ashing processing ranges from 1:0.9 to 1:1.5.