Array Substrate Photoresist Thickness Variation for Narrow Metal Wiring
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Solution Overview
Problem
The increasing demand for large-size, high-pixel-density display products requires narrower metal wiring lines, which contradicts the need for a larger difference in line width between the etched gate electrode and photoresist to prevent wire breaks and ensure conductivity, while also preventing helium plasma and metal atom diffusion during the conductorization process in top-gate type thin film transistors (TFTs).
Innovation Solution
A method for manufacturing an array substrate involving the formation of a conductive material thin film on a base substrate, with a photoresist layer having specific thickness variations to etch the conductive material and gate insulation material, ensuring a large difference in line width between the etched gate electrode and photoresist, and a self-alignment process to protect the gate insulation layer, thereby preventing wire breaks and diffusion issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the metal wiring line width is narrowed to increase pixel density, then the pixel density is improved, but the difference in line width between the etched gate electrode and photoresist is reduced, leading to increased wire break frequency
Solution Approach 1:
The photoresist layer is designed with non-uniform thickness: a first thickness in the gate electrode formation region and a second thickness (greater than the first) in the signal line formation region. This local differentiation allows the photoresist to provide sufficient width difference for etching control in signal line regions while accommodating the narrowed line width requirements for high pixel density.
Solution Approach 2:
The invention changes the thickness parameter of the photoresist layer spatially across different regions of the substrate. By adjusting the photoresist thickness from a first value to a second value (greater than the first) in specific regions, the etching process can maintain adequate width differences even when the final metal wiring lines are narrowed for high pixel density displays.
2Quantity of substance
If the photoresist line width is made close to the gate electrode line width to reduce photoresist width, then the pixel density is improved, but the conductivity of signal lines deteriorates due to insufficient width difference
Solution Approach 1:
The photoresist layer is designed with non-uniform thickness: a first thickness in the gate electrode formation region and a second thickness (greater than the first) in the signal line formation region. This local differentiation allows the photoresist to provide sufficient width difference for etching control in signal line regions while accommodating the narrowed line width requirements for high pixel density displays.
3Quantity of substance
If the photoresist line width is reduced to increase pixel density, then the pixel density is improved, but the protection of gate insulation layer from plasma and metal atom diffusion deteriorates
Solution Approach 1:
The photoresist layer is designed with non-uniform thickness: a first thickness in the gate electrode formation region and a second thickness (greater than the first) in the signal line formation region. This local differentiation allows the photoresist to provide sufficient width difference for etching control in signal line regions while accommodating the narrowed line width requirements for high pixel density displays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the conductivity of signal lines, reduces wire break frequency, and stabilizes TFT characteristics by maintaining the difference in line widths and preventing plasma and metal diffusion, improving display quality and reducing power consumption.
Implementation Method 1
performing an ashing process on the first photoresist layer to remove the third covering portions of the first photoresist layer
Data Source
AI summary
An array substrate, a method for manufacturing the same and a display device are provided. The method includes: providing a base substrate; forming a conductive material thin film on the base substrate; forming a first photoresist layer on a side of the conductive material thin film distal to the base substrate; etching the conductive material thin film by using the first photoresist layer as a mask to obtain a first etched pattern; removing third covering portions of the first photoresist layer to obtain a second photoresist layer; and etching the first etched pattern by using the second photoresist layer as a mask to obtain a gate electrode and a signal line.