Array Substrate for Digital X-Ray Detector PIN Diode Step Difference
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Solution Overview
Problem
Conventional digital X-ray detectors face issues with step differences in PIN diodes leading to crack formation, reduced fill factor, and increased off-current, which affect stack coverage and modulation transfer function (MTF) characteristics.
Innovation Solution
The array substrate design includes a base substrate with an active layer having a channel region, source, and drain regions, where the source region is larger and in surface contact with the lower electrode, minimizing step differences and allowing the PIN diode to be formed over the entire source region, thereby reducing off-current and improving fill factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the PIN diode is formed with a large thickness to improve detection sensitivity, then the detection capability is enhanced, but a large step difference occurs between protective layers causing crack formation and deteriorated stack coverage
Solution Approach 1:
A planarization layer is introduced as an intermediary component between the thick PIN diode and the protective layers. This planarization layer compensates for the step difference created by the thick PIN diode, providing a flat surface for subsequent protective layer deposition and preventing crack formation while maintaining the detection sensitivity benefits of the thick PIN diode structure.
Solution Approach 2:
The protective layer structure is segmented into multiple layers including a planarization layer, first protective layer, and second protective layer. This segmentation allows each layer to serve a specific function: the planarization layer addresses the step difference issue, while the other protective layers provide electrical isolation and mechanical protection, collectively solving the stack coverage problem.
2Reliability
If the lower electrode of the PIN diode is connected to the source electrode through a contact hole, then electrical connection is achieved, but the PIN layer deposited over the bent lower electrode causes bending of the PIN diode lower region leading to increased off-current
Solution Approach 1:
The planarization layer serves as an intermediary that provides a flat deposition surface for the PIN layer. This prevents the PIN layer from conformally following the bent lower electrode contour, thereby preventing bending of the PIN diode lower region and reducing off-current while maintaining proper electrical connection through the contact hole structure.
3Area of stationary object
If the contact hole size is reduced to increase the fill factor of the PIN diode, then the aperture ratio is improved, but the lower electrode bending issue persists and off-current increases
Solution Approach 1:
The planarization layer acts as a mediator that decouples the fill factor optimization from the lower electrode bending problem. By providing a flat surface for PIN layer deposition, it allows the contact hole to be minimized for high fill factor while preventing the PIN layer from bending along the lower electrode contour, thus reducing off-current.
4Reliability
If multiple protective layers are formed to cover the PIN diode and bias electrode, then electrical isolation and mechanical protection are provided, but large step differences cause crack formation in the protective layers
Solution Approach 1:
The protective structure is segmented into multiple functional layers: a planarization layer that addresses the step difference issue, a first protective layer that provides electrical isolation, and a second protective layer that provides additional mechanical protection. This segmentation allows each layer to optimize its specific function without compromising the others, preventing crack formation while maintaining electrical isolation.
Solution Approach 2:
The planarization layer serves as an intermediary between the underlying structures with large step differences and the protective layers. It provides a flat surface that prevents stress concentration and crack formation in the protective layers while allowing them to fulfill their electrical isolation and mechanical protection functions.
5Manufacturing precision
If conventional fabrication processes are used with multiple masks for forming protective layers and contact holes, then precise patterning is achieved, but the fabrication complexity and number of process steps increase
Solution Approach 1:
The planarization layer formation is merged with the existing protective layer fabrication process. The same photolithography and etching steps used for forming protective layers are utilized to form the planarization layer, combining multiple functions into a unified process flow and reducing overall fabrication complexity while maintaining patterning precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances stack coverage, reduces crack formation in protective layers, and improves MTF characteristics by minimizing step differences and off-current, while also simplifying the fabrication process by reducing the number of masks needed.
Implementation Method 1
the scintillator 50 converts the incident X-rays into visible light
Implementation Method 2
The visible light applied to the PIN diode 30 is re-converted into an electronic signal in the PIN layer 33
Data Source
AI summary
An array substrate for a digital X-ray detector, a digital X-ray detector including the same, and a method for manufacturing the same are disclosed. The array substrate reduces a step difference of a PIN diode, removes a bent part from a lower part to reduce characteristic deterioration of the PIN diode, and increases the size of a formation region of the PIN diode to increase a fill factor. To this end, the array substrate allows a source region of an active layer included in a thin film transistor to be in surface contact with a lower electrode of the PIN diode, and disposes the lower electrode over a planarized source region or a base substrate, such that a step difference of the PIN diode is reduced and fill factor is improved.