Array Substrate Multi-Row Pixel Segmentation for High Refresh Rate
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Solution Overview
Problem
Current display technologies face challenges in increasing screen refresh rates and ensuring sufficient charging time for pixels, leading to issues like video ghosting and poor display quality due to low refresh rates and insufficient charging time.
Innovation Solution
The array substrate design incorporates multiple rows of pixels connected to different signal lines, allowing simultaneous input of gate and data signals to multiple rows, which doubles the refresh rate and prolongs charging time, thereby enhancing screen refresh speed and preventing display artifacts like horizontal lines and dark areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional single-row pixel configuration is used, then device complexity is low, but screen refresh rate is limited and charging time is insufficient
Solution Approach 1:
The pixel array is segmented into multiple row groups, where odd rows are connected to first signal lines and even rows are connected to second signal lines. This segmentation allows independent signal transmission to different row groups, enabling simultaneous charging of multiple rows and thus doubling the screen refresh rate without proportionally increasing overall system complexity.
Solution Approach 2:
The patent introduces a dimensional differentiation by separating pixel rows into two distinct groups based on their connection to different signal line sets. This dimensional organization (odd/even row separation) enables parallel processing of signal transmission, effectively increasing refresh rate by utilizing the row dimension for parallel charging operations.
2Duration of action of moving object
If traditional single-row pixel configuration is used, then charging time is sufficient for single row, but total charging time becomes insufficient for high refresh rates
Solution Approach 1:
The patent implements preliminary action by pre-establishing separate signal line connections for odd and even rows before the charging process begins. This pre-configuration enables simultaneous signal transmission to multiple rows, allowing the system to charge multiple rows in parallel during each refresh cycle, thus maintaining sufficient charging time even at doubled refresh rates.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining continuous signal transmission to both odd and even rows simultaneously through their respective signal line sets. This continuous parallel charging action eliminates idle time between row charging operations, ensuring that the total charging time remains sufficient even as the refresh rate increases due to the multi-row parallel configuration.
3Productivity
If refresh rate is increased without additional signal lines, then charging time becomes insufficient, but adding more signal lines increases device complexity
Solution Approach 1:
The patent applies universality by designing the signal line configuration to serve multiple functions: the first signal lines simultaneously provide data transmission and charging capability to all odd rows, while the second signal lines do the same for even rows. This multi-functional design enables the system to achieve doubled refresh rate without requiring separate dedicated lines for each function, thus minimizing the increase in device complexity.
Solution Approach 2:
The patent merges the functions of data transmission and charging into a single signal line infrastructure. By combining these functions in the first and second signal lines that serve multiple rows simultaneously, the patent avoids the need for separate transmission and charging lines, thereby achieving high refresh rate with minimal additional complexity compared to a system with fully separate dedicated lines for each function.
Data Source
AI summary
An array substrate includes: gate lines; data lines crossing the gate lines; first additional signal lines crossing the gate lines and an array of pixels, pixels in each of rows of pixels are connected to a same one of the gate lines; and there are one data line and one first additional signal line between any two adjacent columns of pixels; the array comprises first rows of pixels and second rows of pixels, the first pixels in each of first rows of pixels are connected respectively to the data lines, and the second pixels in each of second rows of pixels are connected respectively to the first additional signal lines; the gate lines comprise first gate lines and second gate lines, the first rows of pixels are connected respectively to the first gate lines, and the second rows of pixels are connected respectively to the second gate lines.