Array Substrate Planarization Layer for Aperture Ratio
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Solution Overview
Problem
Conventional LCD device manufacturing processes face challenges with low aperture ratio and surface unevenness due to the use of contact holes, which can lead to bubble formation and reduced reliability.
Innovation Solution
An array substrate is designed with a planarization layer formed by 3D printing using nano-powder or liquid insulating material, allowing for the formation of source and drain electrodes on the planarization layer without through holes, enabling direct connection to the pixel electrode layer and preventing bubble formation, while increasing the aperture ratio and antistatic ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact holes are used to connect pixel electrode layer and drain metal layer, then electrical connection is achieved, but aperture ratio is reduced and surface unevenness occurs leading to bubble formation
Solution Approach 1:
The invention extracts and eliminates the contact hole structure from the device architecture. Instead of creating holes through the pixel electrode layer to achieve electrical connection, the patent uses a planar surface where the pixel electrode layer directly contacts the drain electrode through a conductive connection structure, completely removing the harmful contact hole element while maintaining electrical connectivity
Solution Approach 2:
The invention transitions from a vertical connection approach (through-holes penetrating multiple layers) to a lateral connection approach. The drain electrode extends laterally to directly contact the pixel electrode layer on the planar surface, changing the connection dimension from vertical (through z-axis holes) to horizontal (along x-y plane), thereby eliminating the need for aperture-reducing contact holes
2Reliability
If contact holes are used to ensure electrical connection, then connectivity is achieved, but surface unevenness occurs where bubbles are easily formed
Solution Approach 1:
The invention converts the potential harm of surface unevenness into a benefit by deliberately designing a planarized surface structure. The planarization layer fills and flattens any underlying surface irregularities, transforming what would be harmful unevenness into a beneficial smooth surface that prevents bubble formation while maintaining electrical connection functionality
Solution Approach 2:
The invention introduces a planarization layer as an intermediary element between the substrate and the electrode layers. This intermediate layer serves as a mediator that provides a smooth planar surface for electrode deposition, preventing direct contact between bubbles and the electrode structure while maintaining the electrical connection pathway
3Ease of manufacture
If conventional manufacturing process with contact holes is used, then device fabrication is achieved, but aperture ratio remains low
Solution Approach 1:
The invention changes the critical parameter of surface topology from uneven (with contact holes) to planar. By modifying the surface parameter through the planarization layer and adopting a planar electrode contact architecture, the aperture ratio parameter is significantly increased while the manufacturing process remains feasible through standard thin-film deposition and patterning techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the aperture ratio and prevents bubble formation near through holes, improving electrical connectivity and antistatic properties by eliminating the need for contact holes and allowing direct formation of the pixel electrode layer on the planarization layer.
Implementation Method 1
the planarization layer is formed by 3D printing using nano-powder material or liquid insulating material
Implementation Method 2
an amorphous silicon layer deposited on the first insulating layer
Data Source
AI summary
An array substrate and a manufacturing method thereof are disclosed. The array substrate includes: a glass substrate; a gate electrode; a first insulating layer; a semiconductor layer; a planarization layer mounted on the first insulating layer; a source electrode and a drain electrode; a pixel electrode layer mounted on the planarization layer and the drain electrode; a second insulating layer mounted on the planarization layer, the semiconductor layer, the source electrode and the drain electrode. The array substrate can prevent bubbles from forming at through holes and thereby increasing aperture ratio. The planarization layer further increases distances between the source electrode, the drain electrode and the gate electrode, which enhances antistatic ability.


